Patents by Inventor Sean Lau
Sean Lau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240381524Abstract: A shock absorber for a printed circuit board (PCB) includes a first portion and a second portion. The first portion is positioned on a first side of the PCB at or near a connector that extends from the PCB. The second portion is positioned on a second side of the PCB, opposite the first portion. The first and second portions prevent the PCB from moving when the PCB is coupled to a host device. As the PCB is subjected to various movements, strains and stresses, the shock absorber prevents the PCB from cracking or breaking, especially at or near the connector, which is susceptible to cracking and breaking.Type: ApplicationFiled: July 24, 2023Publication date: November 14, 2024Inventors: MyungJin Kim, Fu Xing Chan, Chun Sean Lau, Lihwa Fong
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Publication number: 20240260194Abstract: A semiconductor storage device such as an SSD includes a pliable printed circuit board (PCB) having semiconductor memory devices mounted by solder balls on first and second opposed major surfaces. The memory devices are mounted so as to be staggered and/or partially overlapping with each other on the first and second surfaces of the PCB in at least one direction. The staggered arrangement allows the PCB to flex upon warping of the memory devices mounted on the PCB.Type: ApplicationFiled: July 17, 2023Publication date: August 1, 2024Applicant: Western Digital Technologies, Inc.Inventors: Fu Xing Chan, Chun Sean Lau, Bo Yang
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Publication number: 20240260237Abstract: A semiconductor storage device includes semiconductor packages mounted on a printed circuit board (PCB) and encased within an enclosure. The semiconductor storage device includes thermal interface material mounted on side edges of the PCB. During depaneling (separation) of individual semiconductor storage devices from a PCB panel, edges of the PCB may be overcut to expose thermally conductive edge layers provided within the interior the PCB. The thermal interface material may be positioned adjacent to the exposed thermally conductive edge layers to conduct heat away from a semiconductor package through the side edges of the PCB and out of sides of the enclosure.Type: ApplicationFiled: July 17, 2023Publication date: August 1, 2024Applicant: Western Digital Technologies, Inc.Inventors: Wei Hong Tew, Chun Sean Lau, Tze Ping Chan
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Patent number: 12016111Abstract: A protective enclosure for a PCB assembly, e.g., a solid-state-drive assembly. In an example embodiment, the enclosure comprises a flexible, stamped-metal heat spreader connected, by way of cured-liquid TIM parts, to at least some of the packaged integrated circuits on one side of the PCB assembly. In some embodiments, additional cured-liquid TIM parts may be connected between the body of the protective enclosure and packaged integrated circuits on the other side of the PCB assembly and/or the assembly's PCB. The PCB assembly, heat spreader, and various TIM parts are arranged in a manner that helps to significantly lower the risk of solder-joint failure under thermal cycling.Type: GrantFiled: April 20, 2022Date of Patent: June 18, 2024Assignee: Western Digital Technologies, Inc.Inventors: Chun Sean Lau, Ahmad Faridzul Hilmi Shamsuddin, Bo Yang, Shankara Venkatraman Gopalan, Warren Middlekauff, Ning Ye
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Patent number: 11985782Abstract: A data storage device includes an enclosure and a Printed Circuit Board Assembly (PCBA) extending in a basal plane, and a plurality of semiconductor memory packages electromechanically bonded to the PCBA and coupled to the enclosure with thermal interface material. The data storage device further includes a first fitting coupled to a first end of the PCBA and the enclosure, restricting movement of the PCBA in the basal plane with respect to the enclosure and restricting movement of the PCBA out of the basal plane. The data storage device further includes a second fitting coupled to a second end of the PCBA, allowing movement of the PCBA in the basal plane with respect to the enclosure and restricting movement of the PCBA out of the basal plane.Type: GrantFiled: April 8, 2022Date of Patent: May 14, 2024Assignee: Western Digital Technologies, Inc.Inventors: Bo Yang, Warren Middlekauff, Sean Lau, Ning Ye, Shrikar Bhagath, Yangming Liu
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Publication number: 20230345614Abstract: A protective enclosure for a PCB assembly, e.g., a solid-state-drive assembly. In an example embodiment, the enclosure comprises a flexible, stamped-metal heat spreader connected, by way of cured-liquid TIM parts, to at least some of the packaged integrated circuits on one side of the PCB assembly. In some embodiments, additional cured-liquid TIM parts may be connected between the body of the protective enclosure and packaged integrated circuits on the other side of the PCB assembly and/or the assembly’s PCB. The PCB assembly, heat spreader, and various TIM parts are arranged in a manner that helps to significantly lower the risk of solder-joint failure under thermal cycling.Type: ApplicationFiled: April 20, 2022Publication date: October 26, 2023Inventors: Chun Sean Lau, Ahmad Faridzul Hilmi Shamsuddin, Bo Yang, Shankara Venkatraman Gopalan, Warren Middlekauff, Ning Ye
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Publication number: 20230328910Abstract: A data storage device includes an enclosure and a Printed Circuit Board Assembly (PCBA) extending in a basal plane, and a plurality of semiconductor memory packages electromechanically bonded to the PCBA and coupled to the enclosure with thermal interface material. The data storage device further includes a first fitting coupled to a first end of the PCBA and the enclosure, restricting movement of the PCBA in the basal plane with respect to the enclosure and restricting movement of the PCBA out of the basal plane. The data storage device further includes a second fitting coupled to a second end of the PCBA, allowing movement of the PCBA in the basal plane with respect to the enclosure and restricting movement of the PCBA out of the basal plane.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Applicant: Western Digital Technologies, Inc.Inventors: Bo Yang, Warren Middlekauff, Sean Lau, Ning Ye, Shrikar Bhagath, Yangming Liu
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Patent number: 11551991Abstract: A packaged semiconductor device includes a substrate, a heat-generating component positioned on a surface of the substrate, an enclosure at least partially surrounding the substrate and the heat-generating component, and a thermal interface material disposed between the heat-generating component and the enclosure. The enclosure includes a cover portion having a convexly curved surface configured to apply a pressure to the thermal interface material. The pressure may be substantially uniform over the area of the thermal interface material, or may be higher at a center of the thermal interface material than at a periphery of the thermal interface material.Type: GrantFiled: June 5, 2020Date of Patent: January 10, 2023Assignee: Western Digital Technologies, Inc.Inventors: Bo Yang, Chun Sean Lau, Ning Ye, Shrikar Bhagath
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Publication number: 20220378442Abstract: Devices and methods are provided that simplify and improve placement of stabilizing orthopedic pins, wires, and/or screws in the pelvis in minimally invasive surgery. Provided is a surgical instrument guide containing an adjustable friction clamp for positioning and securing a cannula, and a probe with a blunt, nonpenetrating tip. The probe and a surgical instrument held by the friction clamp are oriented at right angles to one another. In use, the blunt probe is introduced through a small incision and advanced by blunt dissection until the blunt tip is positioned at a desired anatomical landmark on the surface of the pelvis. A cannula inserted through the friction clamp is advanced until the tip of the cannula is within 2 cm of the blunt tip of the probe; an orthopedic pin, wire, and/or screw can then be inserted through the cannula to provide stabilization. The blunt probe may be cannulated.Type: ApplicationFiled: November 8, 2019Publication date: December 1, 2022Inventors: Christian Xinshuo Fang, Kenneth Man-Chee Cheung, Kenny Yat Hong Kwan, Gar Hay Felix Sean Lau
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Patent number: 11284502Abstract: A multi-layer printed circuit board (PCB) has a bonding surface disposed on a first surface and a first thermal relief pad disposed on the first surface and surrounding the bonding surface. A first conductive plane on the first surface partially surrounds the first thermal relief pad. The first conductive plane is connected to the bonding surface by one or more first spokes. A second thermal relief pad is disposed on the first surface and partially surrounds the first conductive plane. A second conductive plane is disposed on the first surface and surrounds the second thermal relief pad. The second conductive plane is connected to the first conductive plane by one or more second spokes. A through hole is located in the bonding surface for receiving an electrical connector of an electronic component.Type: GrantFiled: February 11, 2020Date of Patent: March 22, 2022Assignee: Western Digital Technologies, Inc.Inventors: Chun Sean Lau, Choon Kuai Lee, Ing Chyuan Ooi
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Patent number: 11264301Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.Type: GrantFiled: March 17, 2020Date of Patent: March 1, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
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Publication number: 20210384099Abstract: A packaged semiconductor device includes a substrate, a heat-generating component positioned on a surface of the substrate, an enclosure at least partially surrounding the substrate and the heat-generating component, and a thermal interface material disposed between the heat-generating component and the enclosure. The enclosure includes a cover portion having a convexly curved surface configured to apply a pressure to the thermal interface material. The pressure may be substantially uniform over the area of the thermal interface material, or may be higher at a center of the thermal interface material than at a periphery of the thermal interface material.Type: ApplicationFiled: June 5, 2020Publication date: December 9, 2021Applicant: Western Digital Technologies, Inc.Inventors: Bo Yang, Chun Sean Lau, Ning Ye, Shrikar Bhagath
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Patent number: 11094604Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.Type: GrantFiled: June 27, 2019Date of Patent: August 17, 2021Assignee: Western Digital Technologies, Inc.Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
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Publication number: 20210251068Abstract: A multi-layer printed circuit board (PCB) has a bonding surface disposed on a first surface and a first thermal relief pad disposed on the first surface and surrounding the bonding surface. A first conductive plane on the first surface partially surrounds the first thermal relief pad. The first conductive plane is connected to the bonding surface by one or more first spokes. A second thermal relief pad is disposed on the first surface and partially surrounds the first conductive plane. A second conductive plane is disposed on the first surface and surrounds the second thermal relief pad. The second conductive plane is connected to the first conductive plane by one or more second spokes. A through hole is located in the bonding surface for receiving an electrical connector of an electronic component.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Applicant: Western Digital Technologies, Inc.Inventors: Chun Sean Lau, Choon Kuai Lee, Ing Chyuan Ooi
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Publication number: 20200219787Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.Type: ApplicationFiled: March 17, 2020Publication date: July 9, 2020Inventors: Lee Kong YU, Sungjun IM, Chun Sean LAU, Yoong Tatt CHIN, Paramjeet Singh GILL, Weng-Hong TEH
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Patent number: 10636722Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.Type: GrantFiled: September 26, 2017Date of Patent: April 28, 2020Assignee: Western Digital Technologies, Inc.Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
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Publication number: 20190326194Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.Type: ApplicationFiled: June 27, 2019Publication date: October 24, 2019Inventors: Lee Kong YU, Sungjun IM, Chun Sean LAU, Yoong Tatt CHIN, Paramjeet Singh GILL, Weng-Hong TEH
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Publication number: 20190096783Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.Type: ApplicationFiled: September 26, 2017Publication date: March 28, 2019Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh