Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.

Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.

Abstract: A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the gate stack of a first transistor to provide a continuous electrical flowpath over a gate electrode of the first transistor and the source or drain region of a second transistor.

Abstract: A semiconductor structure is provided which eliminates the contact resistance traditionally associated with a junction between one or more contacts and a buried conductive structure formed in the semiconductor structure. The semiconductor structure includes a first insulating layer formed on a semiconductor layer and a conductive structure formed on at least a portion of the first insulating layer. A second insulating layer is formed on at least a portion of the conductive structure. At least one contact is formed through the second insulating layer and electrically connected to the conductive structure. The contact and the conductive structure are formed as a substantially homogeneous structure in a same processing step.

Abstract: An integrated circuit having an integrated circuit die and at least one height-sensing pad disposed on a top surface of the integrated circuit die and electrically isolated from the die circuitry. At least one bond pad is disposed on a top surface of the integrated circuit die and electrically connected to the die circuitry. The at least one bond pad is configured for wire-bonding to a lead of a leadframe utilizing a height coordinate of the at least one height-sensing pad.

Abstract: A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the gate stack of a first transistor to provide a continuous electrical flowpath over a gate electrode of the first transistor and the source or drain region of a second transistor.

Abstract: An integrated manufacturing system comprising: providing a substrate; forming a gate over the substrate; measuring a gate length of the gate; forming a first spacer adjacent the gate; measuring a spacer critical dimension of the spacer; and adjusting a dose of an implant based on the gate length and the spacer critical dimension for a source/drain region.

Abstract: A semiconductor structure is provided which eliminates the contact resistance traditionally associated with a junction between one or more contacts and a buried conductive structure formed in the semiconductor structure. The semiconductor structure includes a first insulating layer formed on a semiconductor layer and a conductive structure formed on at least a portion of the first insulating layer. A second insulating layer is formed on at least a portion of the conductive stricture. At least one contact is formed through the second insulating layer and electrically connected to the conductive structure. The contact and the conductive structure are formed as a substantially homogeneous structure in a same processing step.

Abstract: Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 ?m in height and advantageously within 100 ?m of another such non-planarity. Such non-planarities, it is contemplated, reduce grain boundary movement in the overlying interconnect with a concomitant reduction in void aggregation.

Abstract: A method of forming a buried conductive structure in a semiconductor device includes the steps of forming a first insulating layer on a semiconductor layer; forming a sacrificial structure on at least a portion of the first insulating layer; forming a second insulating layer on at least a portion of the sacrificial structure; forming at least one opening through the second insulating layer to at least partially expose the sacrificial structure; substantially removing the sacrificial structure, leaving a cavity; and substantially filling the cavity and the at least one opening with a conductive material. The sacrificial structure may be substantially removed by etching the sacrificial structure using an isotropic etchant.

Abstract: A method of forming a buried conductive structure in a semiconductor device includes the steps of forming a first insulating layer on a semiconductor layer; forming a sacrificial structure on at least a portion of the first insulating layer; forming a second insulating layer on at least a portion of the sacrificial structure; forming at least one opening through the second insulating layer to at least partially expose the sacrificial structure; substantially removing the sacrificial structure, leaving a cavity; and substantially filling the cavity and the at least one opening with a conductive material. The sacrificial structure may be substantially removed by etching the sacrificial structure using an isotropic etchant.

Abstract: An integrated circuit having an integrated circuit die and at least one height-sensing pad disposed on a top surface of the integrated circuit die and electrically isolated from the die circuitry. At least one bond pad is disposed on a top surface of the integrated circuit die and electrically connected to the die circuitry. The at least one bond pad is configured for wire-bonding to a lead of a leadframe utilizing a height coordinate of the at least one height-sensing pad.

Abstract: Methods and apparatus for performing a wire-bonding operation in an integrated circuit are disclosed. The positions of at least one height-sensing pad and at least one bond pad are determined on a top surface of an integrated circuit die. The height-sensing pad is electrically isolated from the die circuitry and the bond pad is electrically connected to the die circuitry. A bonding tool is lowered to the height-sensing pad, and a height coordinate of the height-sensing pad is then determined. Finally, the bond pad is wire-bonded to a leadframe utilizing the height coordinate of the height-sensing pad.

Abstract: Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 ?m in height and advantageously within 100 ?m of another such non-planarity. Such non-planarities, it is contemplated, reduce grain boundary movement in the overlying interconnect with a concomitant reduction in void aggregation.

Abstract: A method of forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on at least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench through the epitaxial layer to at least partially expose the substrate. The method further includes doping at least one or more sidewalls of the at least one trench with an impurity of a known concentration level. The at least one trench is then substantially filled with a filler material. In this manner, a low-resistance electrical path is formed between an upper surface of the epitaxial layer and the substrate.

Abstract: Techniques for detecting damage on an integrated circuit die using a particle suspension solution are disclosed. The particles of the suspension solution preferentially attach to damaged regions on exposed dielectric films or other portions of the die. For example, one aspect of the invention is a method of detecting damage to a dielectric film used in fabricating a die of an integrated circuit. A particle suspension solution is applied to the die and damaged regions of the dielectric film are identified as areas having an accumulation of particles of the particle suspension solution.

Abstract: Techniques for detecting damage on an integrated circuit die using a particle suspension solution are disclosed. The particles of the suspension solution preferentially attach to damaged regions on exposed dielectric films or other portions of the die. For example, one aspect of the invention is a method of detecting damage to a dielectric film used in fabricating a die of an integrated circuit. A particle suspension solution is applied to the die and damaged regions of the dielectric film are identified as areas having an accumulation of particles of the particle suspension solution.

Abstract: A method of forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on at least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench through the epitaxial layer to at least partially expose the substrate. The method further includes doping at least one or more sidewalls of the at least one trench with an impurity of a known concentration level. The at least one trench is then substantially filled with a filler material. In this manner, a low-resistance electrical path is formed between an upper surface of the epitaxial layer and the substrate.