Abstract: Described herein are examples of interfaces for designing and/or configuring custom assisted defect recognition (ADR) systems and/or workflows. In some examples, the ADR systems and/or workflows may be designed and/or configured using visual tools, such as, for example, node based processing tools. In some examples, the ADR workflows may be used to analyze two dimensional (2D) and/or three dimensional (3D) image scans, such as might be generated by industrial X-ray scanning systems.

Abstract: A system for non-destructive evaluation of an object uses a spherical coordinate system to control two robotic arms. In some examples, the system includes a radiation source coupled to one robotic arm, a radiation detector coupled to the other robotic arm; and a control unit configured to determine, based on input, a first position located on a first surface of a first sphere within the spherical coordinate system; determine, based on the input, a second position located on a second surface of a second sphere within the spherical coordinate system, wherein the second position is located opposite a midpoint of the spherical coordinate system from the first position; and control a motion of the source robotic arm and the detector robotic arm such that the radiation source and the radiation detector move to different ones of the first position and the second position.

Abstract: Described herein are examples of interfaces for designing and/or configuring custom assisted defect recognition (ADR) systems and/or workflows. In some examples, the ADR systems and/or workflows may be designed and/or configured using visual tools, such as, for example, node based processing tools. In some examples, the ADR workflows may be used to analyze two dimensional (2D) and/or three dimensional (3D) image scans, such as might be generated by industrial X-ray scanning systems.

Abstract: A system for non-destructive evaluation of an object uses a spherical coordinate system to control two robotic arms. In some examples, the system includes a radiation source coupled to one robotic arm, a radiation detector coupled to the other robotic arm; and a control unit configured to determine, based on input, a first position located on a first surface of a first sphere within the spherical coordinate system; determine, based on the input, a second position located on a second surface of a second sphere within the spherical coordinate system, wherein the second position is located opposite a midpoint of the spherical coordinate system from the first position; and control a motion of the source robotic arm and the detector robotic arm such that the radiation source and the radiation detector move to different ones of the first position and the second position.

Abstract: The various embodiments provide a semiconductor chip holder that holds semiconductor chips. The chip holder protects the semiconductor chips from possible damage during transport and/or storage. The chip holder is flexible and may be wound around a reel for convenient transport and storage. In one embodiment, the chip holder includes a support substrate with receptacles that receive semiconductor chips, a cover layer that seals the receptacles and holds the semiconductor chips within the receptacles, and plugs to securely couple the support substrate and the cover layer together.

Abstract: The various embodiments provide a semiconductor chip holder that holds semiconductor chips. The chip holder protects the semiconductor chips from possible damage during transport and/or storage. The chip holder is flexible and may be wound around a reel for convenient transport and storage. In one embodiment, the chip holder includes a support substrate with receptacles that receive semiconductor chips, a cover layer that seals the receptacles and holds the semiconductor chips within the receptacles, and plugs to securely couple the support substrate and the cover layer together.

Abstract: Provided are methods for fabricating transistors using a gate last approach. These methods involve etching of titanium nitride and titanium carbide structures while preserving high k-dielectric structures. The titanium carbide structures may also include aluminum. Etching may be performed in one or more etching solutions, each including hydrogen peroxide. Titanium nitride and titanium carbide structures can be etched simultaneously (non-selectively) in the same etching solution that also includes hydrochloric acid, in addition to hydrogen peroxide, and maintained at about 25° C. and 85° C. In some embodiments, titanium nitride structures and titanium carbide structures may be etched separately (selectively) in different operations and using different etching solutions. The titanium nitride structures may be etched in a diluted hydrogen peroxide solution maintained at about 25° C. and 85° C.

Abstract: A digital microscope slide image tiling server 16 divides digital microscope slide image 24 into tiles 28. Each tile 28 is labeled with a magnification level and a location relative to the digital microscope slide image 24 that each tile 28 originated. A communications device 20 receives a pathologist selection 40 that designates a portion of a specimen to view at a different magnification. The communications device 20 provides the magnification level and location 44 to the digital microscope slide image tiling server 16. The digital microscope slide image tiling server 16 provides the tiles 38 labeled with the magnification level and location provided by the pathologist selection 40 to the communications device 20. The communications device 20 correlates the coordinate set associated with each tile 38 to the viewer interface of the communications device 20. The communications device 20 displays the tiles 38 via the viewer interface.

Abstract: Particle-clean formulations and methods for semiconductor substrates use aqueous solutions of tetraethylammonium hydroxide (“TEAH,” C8H21NO) with or without hydrogen peroxide (H2O2). The solution pH ranges from 8-12.5. At process temperatures between 20-70 C, the TEAH solutions have been observed to remove particles from silicon-germanium (SiGe) with 20-99% Ge content in 15-300 seconds with very little etching (SiGe etch rates<1 nm/min).

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract: Provided are methods for fabricating transistors using a gate last approach. These methods involve etching of titanium nitride and titanium carbide structures while preserving high k-dielectric structures. The titanium carbide structures may also include aluminum. Etching may be performed in one or more etching solutions, each including hydrogen peroxide. Titanium nitride and titanium carbide structures can be etched simultaneously (non-selectively) in the same etching solution that also includes hydrochloric acid, in addition to hydrogen peroxide, and maintained at about 25° C. and 85° C. In some embodiments, titanium nitride structures and titanium carbide structures may be etched separately (selectively) in different operations and using different etching solutions. The titanium nitride structures may be etched in a diluted hydrogen peroxide solution maintained at about 25° C. and 85° C.

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract: A method includes forming a trench/via in a layer of insulating material, forming a first layer comprised of silicon or germanium on the insulating material in the trench/via, forming a copper-based seed layer on the first layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure.