Abstract: A multi-core audio processor includes an audio fabric block configured to organize data received from a plurality of audio interfaces into streams for processing by a plurality of digital signal processing cores. The plurality of digital signal processing cores include a single sample processing core and a frame processing core. The multi-core audio processor also includes a pool of undedicated random access memory (RAM) and a main controller configured to dynamically allocate memory resources from the pool of undedicated RAM amongst one or more of the plurality of digital signal processing cores.

Abstract: A multi-core audio processor includes an audio fabric block configured to organize data received from a plurality of audio interfaces into streams for processing by a plurality of digital signal processing cores. The plurality of digital signal processing cores include a single sample processing core and a frame processing core. The multi-core audio processor also includes a pool of undedicated random access memory (RAM) and a main controller configured to dynamically allocate memory resources from the pool of undedicated RAM amongst one or more of the plurality of digital signal processing cores.

Abstract: Provided are systems and methods for reducing end-to-end latency. An example method includes configuring an interface, between a codec and a baseband or application processor, to operate in a burst mode. Using the burst mode, a transfer of real-time data is performed between the codec and the baseband or application processor at a high rate. The high rate is defined as rate faster than a real-time rate. The exemplary method includes padding data in a time period remaining after the transfer, at the high rate, of a sample of the real-time data samples. The padded of the data may be configured such that data can be ignored by the receiving component. The interface can include a Serial Low-power Inter-chip Media Bus (SLIMBus). Power consumption may be reduced for the SLIMBus by utilizing the gear shifting or clock stopping SLIMbus features.