Patents by Inventor Sean Michael Carey
Sean Michael Carey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953982Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.Type: GrantFiled: July 19, 2022Date of Patent: April 9, 2024Assignee: International Business Machines CorporationInventors: Alejandro Alberto Cook Lobo, Andrew A. Turner, Christian Jacobi, Eberhard Engler, Edward C. McCain, Kevin P. Low, Phillip John Restle, Pradeep Bhadravati Parashurama, Tobias Webel, Alper Buyuktosunoglu, Karl Evan Smock Anderson, Sean Michael Carey, Kennedy Cheruiyot, Daniel Kiss, Isidore G. Bendrihem, Ian Krispin Carmichael
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Publication number: 20240028095Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.Type: ApplicationFiled: July 19, 2022Publication date: January 25, 2024Inventors: Tobias Webel, Alejandro Alberto Cook Lobo, Andrew A. Turner, CHRISTIAN JACOBI, Eberhard Engler, Edward C. McCain, Kevin P. Low, Phillip John Restle, Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu, KARL EVAN SMOCK ANDERSON, Sean Michael Carey, KENNEDY CHERUIYOT, Daniel Kiss, Isidore G. Bendrihem, Eric Jason Fluhr, IAN KRISPIN CARMICHAEL, Gregory Scott Still
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Publication number: 20240028447Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.Type: ApplicationFiled: July 19, 2022Publication date: January 25, 2024Inventors: Alejandro Alberto Cook Lobo, Andrew A. Turner, CHRISTIAN JACOBI, Eberhard Engler, Edward C. McCain, Kevin P. Low, Phillip John Restle, Pradeep Bhadravati Parashurama, Tobias Webel, Alper Buyuktosunoglu, KARL EVAN SMOCK ANDERSON, Sean Michael Carey, KENNEDY CHERUIYOT, Daniel Kiss, Isidore G. Bendrihem, IAN KRISPIN CARMICHAEL
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Patent number: 11817697Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.Type: GrantFiled: April 5, 2022Date of Patent: November 14, 2023Assignee: International Business Machines CorporationInventors: Adam Benjamin Collura, Michael Romain, William V. Huott, Pawel Owczarczyk, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Alper Buyuktosunoglu, Tobias Webel, Michael Joseph Cadigan, Jr., Paul Jacob Logsdon, Sean Michael Carey, Stefan Payer, Karl Evan Smock Anderson, Mark Cichanowski
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Publication number: 20230318286Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.Type: ApplicationFiled: April 5, 2022Publication date: October 5, 2023Inventors: Adam Benjamin COLLURA, Michael ROMAIN, William V. HUOTT, Pawel OWCZARCZYK, Christian JACOBI, Anthony SAPORITO, Chung-Lung K. SHUM, Alper BUYUKTOSUNOGLU, Tobias WEBEL, Michael Joseph CADIGAN, JR., Paul Jacob LOGSDON, Sean Michael CAREY, Stefan PAYER, Karl Evan Smock ANDERSON, Mark CICHANOWSKI
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Publication number: 20230281365Abstract: Aspects of the invention include determining a netlist for an integrated circuit design, wherein the netlist includes a design for placement of a plurality of latches, determining a set of timing paths, wherein each timing path includes a capture latch and at least one launch latch connected to a same local clock buffer controller through a local clock buffer OR circuit, calculating a slack value for each timing path, determining one or more candidate timing paths from the set of timing paths, wherein the one or more candidate timing paths have a slack value below a threshold slack value, calculating a score for each candidate timing path based on a count of a number of launch-capture latch pairs, adjusting an interconnect for a first candidate timing path based on the first candidate timing path having a highest score, and generating an updated netlist based on the adjusting the interconnect.Type: ApplicationFiled: March 2, 2022Publication date: September 7, 2023Inventors: Michael Kazda, Sean Michael Carey, Frank J. Musante, Michael Hemsley Wood
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Patent number: 11501047Abstract: A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.Type: GrantFiled: November 22, 2019Date of Patent: November 15, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sean Michael Carey, Richard Frank Rizzolo, Bodo Hoppe, Divya Kumudprakash Joshi, Paul Jacob Logsdon, Sreekala Anandavally, William Rurik
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Publication number: 20210157963Abstract: A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.Type: ApplicationFiled: November 22, 2019Publication date: May 27, 2021Inventors: Sean Michael Carey, Richard Frank Rizzolo, Bodo Hoppe, Divya Kumudprakash Joshi, Paul Jacob Logsdon, Sreekala Anandavally, WILLIAM RURIK
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Patent number: 8185371Abstract: A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.Type: GrantFiled: April 15, 2009Date of Patent: May 22, 2012Assignee: International Business Machines CorporationInventors: Adil Bhanji, Sean Michael Carey, Jack Dilullo, Prashant D Joshi, Don Richard Rozales, Vern Anthony Victoria, Albert Thomas Williams
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Patent number: 8001411Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times itscommencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.Type: GrantFiled: September 24, 2007Date of Patent: August 16, 2011Assignee: International Business Machines CorporationInventors: Sean Michael Carey, William Vincent Huott, Christian Jacobi, Guenter Mayer, Timothy Gerard McNamara, Chung-Lung Kevin Shum, Hans-Werner Tast, Michael Hemsley Wood
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Publication number: 20100268522Abstract: A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.Type: ApplicationFiled: April 15, 2009Publication date: October 21, 2010Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM CorporationInventors: Adil Bhanji, Sean Michael Carey, Jack Dilullo, Prashant D Joshi, Don Richard Rozales, Vern Anthony Victoria, Albert Thomas Williams
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Publication number: 20090083569Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.Type: ApplicationFiled: September 24, 2007Publication date: March 26, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sean Michael Carey, William Vincent Huott, Christian Jacobi, Guenter Mayer, Timothy Gerard McNamara, Chung-Lung Kevin Shum, Hans-Werner Tast, Michael Hemsley Wood