Patents by Inventor Sean O. Stalley
Sean O. Stalley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11630480Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.Type: GrantFiled: March 13, 2018Date of Patent: April 18, 2023Assignee: Intel CorporationInventors: David J. Harriman, Debendra Das Sharma, Daniel S. Froelich, Sean O. Stalley
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Patent number: 11593280Abstract: Packets may be compressed based on predictive analyses. For example, in one embodiment, it is determined that an explicit value for a particular header field can be inferred by the receiver agent, a packet header is constructed that either omits the header field or includes a differential value for the header field in lieu of the explicit value for the header field. The packet header may be decompressed upon receipt by deriving the explicit value for the particular header field.Type: GrantFiled: September 9, 2019Date of Patent: February 28, 2023Assignee: Intel CorporationInventor: Sean O. Stalley
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Publication number: 20230035420Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.Type: ApplicationFiled: September 28, 2022Publication date: February 2, 2023Applicant: Intel CorporationInventors: Rajesh M. Sankaran, David J. Harriman, Sean O. Stalley, Rupin H. Vakharwala, Ishwar Agarwal, Pratik M. Marolia, Stephen R. Van Doren
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Publication number: 20230022948Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.Type: ApplicationFiled: September 28, 2022Publication date: January 26, 2023Applicant: Intel CorporationInventors: David J. Harriman, Debendra Das Sharma, Daniel S. Froelich, Sean O. Stalley
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Patent number: 11513979Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.Type: GrantFiled: February 26, 2021Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Rajesh M. Sankaran, David J. Harriman, Sean O. Stalley, Rupin H. Vakharwala, Ishwar Agarwal, Pratik M. Marolia, Stephen R. Van Doren
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Publication number: 20210209037Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.Type: ApplicationFiled: February 26, 2021Publication date: July 8, 2021Applicant: Intel CorporationInventors: Rajesh M. Sankaran, David J. Harriman, Sean O. Stalley, Rupin H. Vakharwala, Ishwar Agarwal, Pratik M. Marolia, Stephen R. Van Doren
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Patent number: 10970238Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.Type: GrantFiled: September 10, 2019Date of Patent: April 6, 2021Assignee: Intel CorporationInventors: Rajesh M. Sankaran, David J. Harriman, Sean O. Stalley, Rupin H. Vakharwala, Ishwar Agarwal, Pratik M. Marolia, Stephen R. Van Doren
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Publication number: 20200004703Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.Type: ApplicationFiled: September 10, 2019Publication date: January 2, 2020Applicant: Intel CorporationInventors: Rajesh M. Sankaran, David J. Harriman, Sean O. Stalley, Rupin H. Vakharwala, Ishwar Agarwal, Pratik M. Marolia, Stephen R. Van Doren
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Publication number: 20190391936Abstract: Packets may be compressed based on predictive analyses. For example, in one embodiment, it is determined that an explicit value for a particular header field can be inferred by the receiver agent, a packet header is constructed that either omits the header field or includes a differential value for the header field in lieu of the explicit value for the header field. The packet header may be decompressed upon receipt by deriving the explicit value for the particular header field.Type: ApplicationFiled: September 9, 2019Publication date: December 26, 2019Applicant: Intel CorporationInventor: Sean O. Stalley
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Publication number: 20190041898Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.Type: ApplicationFiled: March 13, 2018Publication date: February 7, 2019Inventors: David J. Harriman, Debendra Das Sharma, Daniel S. Froelich, Sean O. Stalley
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Patent number: 10191877Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.Type: GrantFiled: December 22, 2015Date of Patent: January 29, 2019Assignee: Intel CorporationInventors: David J. Harriman, Manjari Kulkarni, Akshay G. Pethe, Sean O. Stalley, Mahesh Wagh, Debendra Das Sharma
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Publication number: 20180300264Abstract: Embodiments may include systems and methods for managing a function state of a device when the device is coupled to a processor through a computer bus. An apparatus for computing may include a processor coupled to a computer bus. A system driver may be executed by the processor to identify a function state of a device based on a feedback from a function status register in the device, when the device is coupled to the computer bus. A device may include an interface to be coupled to a computer bus, and a function status register coupled to the interface. The function status register may store information to indicate a function state of the device, and the function state may be accessible by a processor coupled to the function status register through the computer bus. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 15, 2017Publication date: October 18, 2018Inventors: David J. Harriman, Sean O. Stalley
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Publication number: 20170177528Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.Type: ApplicationFiled: December 22, 2015Publication date: June 22, 2017Inventors: David J. Harriman, Manjari Kulkarni, Akshay G. Pethe, Sean O. Stalley, Mahesh Wagh, Debendra Das Sharma
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Patent number: 9680758Abstract: Described is an apparatus which comprises: a transmitter; an input-output (I/O) interface coupled to the transmitter; and logic to split data for transmission into a plurality of packets, wherein each packet is stored in a buffer and then transmitted via the I/O interface to a receiver, wherein the logic can vary a number of packets sent prior to the transmitter receiving an Acknowledgement (ACK) signal, and wherein the logic can vary a packet length of the number of packets.Type: GrantFiled: September 2, 2015Date of Patent: June 13, 2017Assignee: Intel CorporationInventor: Sean O. Stalley
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Publication number: 20170063508Abstract: Described is an apparatus which comprises: a transmitter; an input-output (I/O) interface coupled to the transmitter; and logic to split data for transmission into a plurality of packets, wherein each packet is stored in a buffer and then transmitted via the I/O interface to a receiver, wherein the logic can vary a number of packets sent prior to the transmitter receiving an Acknowledgement (ACK) signal, and wherein the logic can vary a packet length of the number of packets.Type: ApplicationFiled: September 2, 2015Publication date: March 2, 2017Inventor: Sean O. Stalley