Patents by Inventor Sean P. Berecek

Sean P. Berecek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cab signal receiver demodulator employing redundant, diverse field programmable gate arrays
    Patent number: 7850127
    Abstract: A processor includes a first field programmable gate array (FPGA) having a first central processing unit (CPU) core programmed to perform a first function, and first programmable hardware logics (PHLs) programmed to perform a second function. A second FPGA includes a second CPU core programmed to perform a third function, and second PHLs programmed to perform a fourth function. A communication interface is between the first and second CPU cores. The first and second FPGAs are diverse. A portion of the first function communicates first information from the first CPU core to the second CPU core through the interface. A portion of the third function communicates second information from the second CPU core to the first CPU core through the interface, and, otherwise, the first function is substantially the same as the third function. The second function is substantially the same as the fourth function.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: December 14, 2010
    Assignee: Ansaldo STS USA, Inc.
    Inventors: John E. Lemonovich, William A. Sharp, James C. Werner, Zhu Ding, Sean P. Berecek
  • CAB SIGNAL RECEIVER DEMODULATOR EMPLOYING REDUNDANT, DIVERSE FIELD PROGRAMMABLE GATE ARRAYS
    Publication number: 20090230255
    Abstract: A processor includes a first field programmable gate array (FPGA) having a first central processing unit (CPU) core programmed to perform a first function, and first programmable hardware logics (PHLs) programmed to perform a second function. A second FPGA includes a second CPU core programmed to perform a third function, and second PHLs programmed to perform a fourth function. A communication interface is between the first and second CPU cores. The first and second FPGAs are diverse. A portion of the first function communicates first information from the first CPU core to the second CPU core through the interface. A portion of the third function communicates second information from the second CPU core to the first CPU core through the interface, and, otherwise, the first function is substantially the same as the third function. The second function is substantially the same as the fourth function.
    Type: Application
    Filed: June 2, 2008
    Publication date: September 17, 2009
    Inventors: John E. Lemonovich, William A. Sharp, James C. Werner, Zhu Ding, Sean P. Berecek