Patents by Inventor Sean R. Atsatt

Sean R. Atsatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12265772
    Abstract: Methods and apparatus for extracting a setting of configuration bits to create an exclusion configuration for providing protection against peek and poke attacks in a multi-tenant usage model of a configurable device is provided. The device may host multiple parties that do not trust each other. Peek and poke attacks are orchestrated by tapping (peeking) and driving (poking) wires associated with other parties. Such attacks may be disabled by excluding the settings of configuration bits that would allow these attacks by other parties. This set of configuration bits that should be excluded for preventing all peek and poke attacks creates the exclusion configuration. Methods are described that disable a particular class of peek and/or poke attacks through the use of partial reconfiguration. Methods and apparatus are described to dynamically detect peek and/or poke attacks.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: April 1, 2025
    Assignee: Altera Corporation
    Inventors: Scott Weber, Sean R. Atsatt, David Goldman
  • Patent number: 12248021
    Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: March 11, 2025
    Assignee: Altera Corporation
    Inventors: Sean R. Atsatt, Ilya K. Ganusov
  • Publication number: 20250077753
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Patent number: 12237831
    Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: February 25, 2025
    Assignee: Intel Corporation
    Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
  • Publication number: 20250036591
    Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
    Type: Application
    Filed: October 10, 2024
    Publication date: January 30, 2025
    Inventors: Ilya K. Ganusov, Ashish Gupta, Chee Hak Teh, Sean R. Atsatt, Scott Jeremy Weber, Parivallal Kannan, Aman Gupta, Gary Brian Wallichs
  • Patent number: 12164462
    Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: December 10, 2024
    Assignee: ALTERA CORPORATION
    Inventors: Ilya K. Ganusov, Ashish Gupta, Chee Hak Teh, Sean R. Atsatt, Scott Jeremy Weber, Parivallal Kannan, Aman Gupta, Gary Brian Wallichs
  • Publication number: 20240396555
    Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.
    Type: Application
    Filed: August 7, 2024
    Publication date: November 28, 2024
    Inventors: Sean R. Atsatt, Scott J. Weber, Ravi Prakash Gutala, Aravind Raghavendra Dasu
  • Publication number: 20240396556
    Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. An n-bit data register (e.g., a 1-bit data register) and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.
    Type: Application
    Filed: August 5, 2024
    Publication date: November 28, 2024
    Inventors: Sean R. Atsatt, Arun Jangity, Thien Le, Simon Chong
  • Patent number: 12153866
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: November 26, 2024
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Patent number: 12063037
    Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: August 13, 2024
    Assignee: Intel Corporation
    Inventors: Sean R. Atsatt, Scott J. Weber, Ravi Prakash Gutala, Aravind Raghavendra Dasu
  • Patent number: 12057836
    Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. An n-bit data register (e.g., a 1-bit data register) and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 6, 2024
    Assignee: Intel Corporation
    Inventors: Sean R Atsatt, Arun Jangity, Thien Le, Simon Chong
  • Publication number: 20240241650
    Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. A quasi-delay insensitive (QDI) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.
    Type: Application
    Filed: March 29, 2024
    Publication date: July 18, 2024
    Inventors: Sean R. Atsatt, Ilya K. Ganusov
  • Patent number: 11960734
    Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. A quasi-delay insensitive (QDI) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: April 16, 2024
    Assignee: Intel Corporation
    Inventors: Sean R Atsatt, Ilya K. Ganusov
  • Publication number: 20230370068
    Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 16, 2023
    Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
  • Publication number: 20230306173
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Application
    Filed: May 31, 2023
    Publication date: September 28, 2023
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Publication number: 20230253965
    Abstract: An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.
    Type: Application
    Filed: April 13, 2023
    Publication date: August 10, 2023
    Inventors: Ravi Prakash Gutala, Aravind Raghavendra Dasu, Sean R. Atsatt, Scott J. Weber
  • Patent number: 11714941
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: August 1, 2023
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, Md Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Patent number: 11700002
    Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: July 11, 2023
    Assignee: Intel Corporation
    Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
  • Patent number: 11632112
    Abstract: An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 18, 2023
    Assignee: Intel Corporation
    Inventors: Ravi Prakash Gutala, Aravind Raghavendra Dasu, Sean R. Atsatt, Scott J. Weber
  • Patent number: 11562101
    Abstract: A programmable logic device verifies that configuration data permissibly programs the programmable logic device. The programmable logic device includes a programmable fabric having partitions to be programmed by the configuration data, a secure device manager that may generate masks based on the configuration data, and a local sector manager. The masks determine that the configuration data is configured to permissibly program the permitted partitions or that the permitted partitions have been permissibly programmed. The local sector manager applies the masks to generate an interleaved result, compares the interleaved result to an expected result, and sends an indication that the configuration data is configured to permissibly program the permitted partitions or permissibly programmed the permitted partitions in response to determining that the interleaved result is the expected result, or sends an alert to stop programming in response to determining that the interleaved result is not the expected result.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 24, 2023
    Assignee: Intel Corporation
    Inventors: Scott J. Weber, Sean R. Atsatt, Andrew Martyn Draper, David Samuel Goldman