Patents by Inventor Sean R. Atsatt

Sean R. Atsatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11115026
    Abstract: An integrated circuit may include multiple programmable logic regions and a first plurality of routers. Each of the first plurality of routers is coupled to a respective region of a first portion of the programmable logic regions, and each of the first portion of the plurality of regions transmits configuration data to a first set of adjacent regions of the first portion of regions. The integrated circuit may also include a second plurality of routers, and each of the second plurality of routers is coupled to a respective region of a second portion of the regions. Each of the second portion of the regions transmits the configuration data to a second set of adjacent regions of the first portion of regions. The integrated circuit may also include a voltage regulator that distributes a voltage to each of the regions.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Sean R. Atsatt, Herman Henry Schmit
  • Patent number: 11080449
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Patent number: 10936511
    Abstract: Systems and methods for providing capability of access to distributed memory blocks using a global address scheme in a programmable logic device. Each of the distributed memory blocks includes routing circuitry that receives data, and in a first mode, decodes whether the data is intended for a respective distributed memory block. In a second mode, the data may bypass routing circuitry. Furthermore, the data may be received at the distributed memory block via cascade connections of distributed memory blocks in a column and/or via register in the programmable fabric of the programmable logic device.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Sean R. Atsatt, Chee Hak Teh
  • Publication number: 20210011636
    Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. A quasi-delay insensitive (QDI) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: Sean R. Atsatt, Ilya K. Ganusov
  • Publication number: 20210013885
    Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. An n-bit data register (e.g., a 1-bit data register) and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: Sean R. Atsatt, Arun Jangity, Thien Le, Simon Chong
  • Publication number: 20210013887
    Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
  • Patent number: 10790827
    Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
  • Publication number: 20200226313
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Patent number: 10659052
    Abstract: Devices and methods for reconfiguring a programmable fabric include identifying resources in a programmable fabric of the programmable device as belonging to a partition. Reconfiguring the programmable fabric also includes creating a mask for the partition that indicates that the identified resources belong to the partition. Reconfiguring the partition also includes reconfiguring resources, via a configuration controller, in programmable fabric associated with the partition using the mask without changing resources associated with other partitions in the programmable fabric.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Sean R. Atsatt, Andrew Draper
  • Publication number: 20200153438
    Abstract: An integrated circuit may include multiple programmable logic regions and a first plurality of routers. Each of the first plurality of routers is coupled to a respective region of a first portion of the programmable logic regions, and each of the first portion of the plurality of regions transmits configuration data to a first set of adjacent regions of the first portion of regions. The integrated circuit may also include a second plurality of routers, and each of the second plurality of routers is coupled to a respective region of a second portion of the regions. Each of the second portion of the regions transmits the configuration data to a second set of adjacent regions of the first portion of regions. The integrated circuit may also include a voltage regulator that distributes a voltage to each of the regions.
    Type: Application
    Filed: January 20, 2020
    Publication date: May 14, 2020
    Inventors: Sean R. Atsatt, Herman Henry Schmit
  • Patent number: 10642946
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, Md Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Publication number: 20200136624
    Abstract: Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires, configuration bits for storing configurations for the functional blocks and routing wires, and local control circuitry for interfacing with the configuration bits to configure the sector. The programmable circuit may include global control circuitry for interfacing with the local control circuitry to configure the sector. Each sector may be independently operable and/or operable in parallel with other sectors. Operating the programmable circuit may include using the local control circuitry to interface with the configurations bit and configure the sector. Additionally, operating the programmable circuit may include using the global control circuitry to interface with respective local control circuitry and configure the sector.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Dana How, Sean R. Atsatt, Michael David Hutton, Herman Henry Schmit
  • Patent number: 10587273
    Abstract: An integrated circuit may include multiple programmable logic regions and a first plurality of routers. Each of the first plurality of routers is coupled to a respective region of a first portion of the programmable logic regions, and each of the first portion of the plurality of regions transmits configuration data to a first set of adjacent regions of the first portion of regions. The integrated circuit may also include a second plurality of routers, and each of the second plurality of routers is coupled to a respective region of a second portion of the regions. Each of the second portion of the regions transmits the configuration data to a second set of adjacent regions of the first portion of regions. The integrated circuit may also include a voltage regulator that distributes a voltage to each of the regions.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 10, 2020
    Assignee: INTEL CORPORATION
    Inventors: Sean R. Atsatt, Herman Henry Schmit
  • Patent number: 10523207
    Abstract: Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires, configuration bits for storing configurations for the functional blocks and routing wires, and local control circuitry for interfacing with the configuration bits to configure the sector. The programmable circuit may include global control circuitry for interfacing with the local control circuitry to configure the sector. Each sector may be independently operable and/or operable in parallel with other sectors. Operating the programmable circuit may include using the local control circuitry to interface with the configurations bit and configure the sector. Additionally, operating the programmable circuit may include using the global control circuitry to interface with respective local control circuitry and configure the sector.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: December 31, 2019
    Assignee: Altera Corporation
    Inventors: Dana How, Sean R. Atsatt, Michael David Hutton, Herman Henry Schmit
  • Publication number: 20190327176
    Abstract: Systems and methods are provided herein for providing an NoC including a configurable array of nodes, where a node of the configurable array of nodes operates in a default operating mode until a replacement operating mode is triggered. For example, when an NoC is unconfigured, a latch bank may be initialized to “clear,” such that no routing decisions are stored. This may enable a default operating mode where routing logic updates the latches' values as needed to implement required routing behavior in a dynamic fashion until configuration is performed.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 24, 2019
    Inventors: Dana How, Herman Henry Schmit, Sean R. Atsatt
  • Patent number: 10446202
    Abstract: Methods and devices for increasing error detection rate while avoiding excessive power distribution network noise are provided. In one method, memory reads of configuration memory of a first group of sectors of a programmable logic device are performed. The memory reads start at a first start time within a first memory read period. The first memory read period includes an amount of time involved to perform one of the memory reads. The method also includes performing memory reads of configuration memory of a second group of sectors of the programmable logic device. The memory reads of the configuration memory of the second group of sectors start at a second start time within the first memory read period. The second start time is different from the first start time. By offsetting the start times of memory reads, power distribution noise may be reduced.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: October 15, 2019
    Assignee: Altera Corporation
    Inventor: Sean R. Atsatt
  • Patent number: 10367745
    Abstract: Systems and methods are provided herein for providing an NoC including a configurable array of nodes, where a node of the configurable array of nodes operates in a default operating mode until a replacement operating mode is triggered. For example, when an NoC is unconfigured, a latch bank may be initialized to “clear,” such that no routing decisions are stored. This may enable a default operating mode where routing logic updates the latches' values as needed to implement required routing behavior in a dynamic fashion until configuration is performed.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: July 30, 2019
    Assignee: Altera Corporation
    Inventors: Dana How, Herman Henry Schmit, Sean R. Atsatt
  • Publication number: 20190199354
    Abstract: Devices and methods for reconfiguring a programmable fabric include identifying resources in a programmable fabric of the programmable device as belonging to a partition. Reconfiguring the programmable fabric also includes creating a mask for the partition that indicates that the identified resources belong to the partition. Reconfiguring the partition also includes reconfiguring resources, via a configuration controller, in programmable fabric associated with the partition using the mask without changing resources associated with other partitions in the programmable fabric.
    Type: Application
    Filed: February 15, 2019
    Publication date: June 27, 2019
    Inventors: Sean R. Atsatt, Andrew Draper
  • Publication number: 20190165789
    Abstract: An integrated circuit may include multiple programmable logic regions and a first plurality of routers. Each of the first plurality of routers is coupled to a respective region of a first portion of the programmable logic regions, and each of the first portion of the plurality of regions transmits configuration data to a first set of adjacent regions of the first portion of regions. The integrated circuit may also include a second plurality of routers, and each of the second plurality of routers is coupled to a respective region of a second portion of the regions. Each of the second portion of the regions transmits the configuration data to a second set of adjacent regions of the first portion of regions. The integrated circuit may also include a voltage regulator that distributes a voltage to each of the regions.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 30, 2019
    Inventors: Sean R. Atsatt, Herman Henry Schmit
  • Publication number: 20190138680
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang