Abstract: A built-in self test (IBIST) architecture/methodology is provided for testing the functionality of an interconnect (such as a bus) between two components. This IBIST architecture may include a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

Abstract: A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.

Abstract: A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.

Abstract: A built-in self test (IBIST) architecture/methodology is provided for testing the functionality of an interconnect (such as a bus) between two components. This IBIST architecture may include a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

Abstract: An integrated circuit (IC) component of a computer system, intended for use as part of a production version of the system, is provided with a built-in test unit and core function circuitry that are coupled to transfer information over the same I/O buffer circuitry of the component. The test unit is to transfer test information during a test session and to recognize announcement of the test session via an assertion and a deassertion, for predetermined time intervals, of an inter-component signal.

Abstract: A method and devices for a current dump circuit that includes a first termination device, a second termination device, and a current dump device. The first termination device resides outside the die of an IC. One end of the first termination device is operatively connected to a first voltage regulator. Another end of the first termination is device operatively connected to a signal line of the IC. The second termination device resides on a die of the IC. One end of the second termination device is operatively connected to a second voltage regulator. Another end of the second termination device is operatively connected to the signal line of the IC. The current dump device provides a path to remove any current flow between the first voltage regulator and the second voltage regulator.

Abstract: An apparatus includes a configuration selector that is selectively configurable to denote one of a plurality of operating modes for the apparatus, including a configuration mode. The apparatus further comprising a programmable multiplexer, a processor, a bus, and a storage medium having stored therein a basic input/output system (BIOS) equipped to operate in any one of the plurality of operating modes, including the configuration mode wherein the BIOS facilitates user programming of a plurality of operating parameters for the apparatus. The programmable multiplexer, responsive to the configuration selector, asserts a default bus/core ratio common to a plurality of processors and buses that can be employed to form the apparatus when the configuration selector is configured to denote the configuration mode of operation. The processor, coupled to the storage medium and the programmable multiplexer, operates to execute the BIOS, in a speed consistent with the asserted bus/core ratio.

Abstract: An apparatus includes a storage medium having stored therein a segmented basic input/output system (BIOS) divided among a plurality of segments within the storage medium, and a processor operative to execute the segmented BIOS. In accordance with the teachings of the present invention, the BIOS includes a recovery function that is mode dependent in that while the apparatus is in an update mode the recovery function executes a full reflash of all relevant segments of the segmented BIOS, whereas while the apparatus is in a normal mode the recovery function executes a partial reflash of only identified corrupted BIOS segments.

Abstract: A dual-in-line Universal Serial Bus (USB) connector including a plurality of USB ports, a plurality of signal pins associated with the ports, and a pair of mounting tabs. The USB connector is adapted for a circuit board including a first footprint for the dual-in-line USB connector situated at a predetermined location of the circuit board. Also, a second footprint is situated at a predetermined location of the circuit board for receipt of a different type of connector instead of the USB connector.

Abstract: An apparatus includes a configuration selector that is selectively configurable to denote one of a plurality of operating modes for the apparatus, including a configuration mode. The apparatus further comprising a programmable multiplexer, a processor, a bus, and a storage medium having stored therein a basic input/output system (BIOS) equipped to operate in any one of the plurality of operating modes, including the configuration mode wherein the BIOS facilitates user programming of a plurality of operating parameters for the apparatus. The programmable multiplexer, responsive to the configuration selector, asserts a default bus/core ratio common to a plurality of processors and buses that can be employed to form the apparatus when the configuration selector is configured to denote the configuration mode of operation. The processor, coupled to the storage medium and the programmable multiplexer, operates to execute the BIOS, in a speed consistent with the asserted bus/core ratio.

Abstract: A dual-in-line Universal Serial Bus connector including a plurality of Universal Serial Bus ports oriented adjacent to each other in a longitudinal direction. The dual-in-line Universal Serial Bus connector further includes a plurality of signal pins and a pair of mounting tabs. The signal pins are coupled to the plurality of Universal Serial Bus ports in order to receive data input into at least one of the plurality of Universal Serial Bus ports. The positioning of the mounting tabs and signal pins enable this connector to be used as a substitute for a serial communication (COM) port connector.