Patents by Inventor Sean S. Kang
Sean S. Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190051557Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.Type: ApplicationFiled: August 13, 2018Publication date: February 14, 2019Inventors: Bencherki MEBARKI, Sean S. KANG, Keith Tatseun WONG, He REN, Mehul B. NAIK, Ellie Y. YIEH, Srinivas D. NEMANI
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Publication number: 20190019681Abstract: The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes supplying an oxygen containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the first and the second layers having a first group and a second group of sidewalls respectively exposed through openings defined in the multi-material layer, maintaining a process pressure at greater than 5 bar, and selectively forming an oxidation layer on the second group of sidewalls in the second layer.Type: ApplicationFiled: July 12, 2017Publication date: January 17, 2019Inventors: Keith Tatseun WONG, Shiyu SUN, Sean S. KANG, Nam Sung KIM, Srinivas D. NEMANI, Ellie Y. YIEH
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Patent number: 10177050Abstract: A dynamically tunable process kit, a processing chamber having a dynamically tunable process kit, and a method for processing a substrate using a dynamically tunable process kit are provided. The dynamically tunable process kit allows one or both of the electrical and thermal state of the process kit to be changed without changing the physical construction of the process kit, thereby allowing plasma properties, and hence processing results, to be easily changed without replacing the process kit. The processing chamber having a dynamically tunable process kit includes a chamber body that includes a portion of a conductive side wall configured to be electrically controlled, and a process kit. The processing chamber includes a first control system operable to control one or both of an electrical and thermal state of the process kit and a second control system operable to control an electrical state of the portion of the side wall.Type: GrantFiled: July 18, 2016Date of Patent: January 8, 2019Assignee: Applied Materials, Inc.Inventors: S. M. Reza Sadjadi, Dmitry Lubomirsky, Hamid Noorbakhsh, John Zheng Ye, David H. Quach, Sean S. Kang
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Publication number: 20180261480Abstract: A high-pressure processing system for processing a substrate includes a first chamber, a pedestal positioned within the first chamber to support the substrate, a second chamber adjacent the first chamber, a vacuum processing system configured to lower a pressure within the second chamber to near vacuum, a valve assembly between the first chamber and the second chamber to isolate the pressure within the first chamber from the pressure within the second chamber, and a gas delivery system configured to introduce a processing gas into the first chamber and to increase the pressure within the first chamber to at least 10 atmospheres while the processing gas is in the first chamber and while the first chamber is isolated from the second chamber.Type: ApplicationFiled: March 9, 2018Publication date: September 13, 2018Inventors: Qiwei LIANG, Srinivas D. NEMANI, Adib KHAN, Venkata Ravishankar KASIBHOTLA, Sultan MALIK, Sean S. KANG, Keith Tatseun WONG
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Publication number: 20170287752Abstract: Embodiments of the disclosure provide an integrated system for performing a measurement process and a lithographic overlay error correction process on a semiconductor substrate in a single processing system. In one embodiment, a processing system includes at least a load lock chamber, a transfer chamber coupled to the load lock chamber, an ion implantation processing chamber coupled to or in the transfer chamber, and a metrology tool coupled to the transfer chamber, wherein the metrology tool is adapted to obtain stress profile or an overlay error on a substrate disposed in the metrology tool.Type: ApplicationFiled: February 28, 2017Publication date: October 5, 2017Inventors: Ludovic GODET, Mehdi VAEZ-IRAVANI, Todd EGAN, Mangesh BANGAR, Concetta RICCOBENE, Abdul Aziz KHAJA, Srinivas D. NEMANI, Ellie Y. YIEH, Sean S. KANG
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Patent number: 9543163Abstract: Methods for etching a material layer disposed on the substrate using a combination of a main etching step and a cyclical etching process are provided. The method includes performing a main etching process in a processing chamber to an oxide layer, forming a feature with a first predetermined depth in the oxide layer, performing a treatment process on the substrate by supplying a treatment gas mixture into the processing chamber to treat the etched feature in the oxide layer, performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process further etches the feature to a second predetermined depth, and performing a transition process on the etched substrate by supplying a transition gas mixture into the processing chamber.Type: GrantFiled: October 21, 2013Date of Patent: January 10, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Mang-Mang Ling, Jungmin Ko, Sean S. Kang, Jeremiah T. Pender, Srinivas D. Nemani, Bradley Howard
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Publication number: 20160329256Abstract: A dynamically tunable process kit, a processing chamber having a dynamically tunable process kit, and a method for processing a substrate using a dynamically tunable process kit are provided. The dynamically tunable process kit allows one or both of the electrical and thermal state of the process kit to be changed without changing the phyisical construction of the process kit, thereby allowing plasma properties, and hence processing results, to be easily changed without replacing the process kit. The processing chamber having a dynamically tunable process kit includes a chamber body that includes a portion of a conductive side wall configured to be electrically controlled, and a process kit. The processing chamber includes a first control system operable to control one or both of an electrical and thermal state of the process kit and a second control system operable to control an electrical state of the portion of the side wall.Type: ApplicationFiled: July 18, 2016Publication date: November 10, 2016Inventors: S. M. Reza SADJADI, Dmitry LUBOMIRSKY, Hamid NOORBAKHSH, John Zheng YE, David H. QUACH, Sean S. KANG
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Patent number: 9412579Abstract: A dynamically tunable process kit, a processing chamber having a dynamically tunable process kit, and a method for processing a substrate using a dynamically tunable process kit are provided. The dynamically tunable process kit allows one or both of the electrical and thermal state of the process kit to be changed without changing the physical construction of the process kit, thereby allowing plasma properties, and hence processing results, to be easily changed without replacing the process kit. The processing chamber having a dynamically tunable process kit includes a chamber body that includes a portion of a conductive side wall configured to be electrically controlled, and a process kit. The processing chamber includes a first control system operable to control one or both of an electrical and thermal state of the process kit and a second control system operable to control an electrical state of the portion of the side wall.Type: GrantFiled: February 13, 2013Date of Patent: August 9, 2016Assignee: Applied Materials, Inc.Inventors: S. M. Reza Sadjadi, Dmitry Lubomirsky, Hamid Noorbakhsh, John Zheng Ye, David H. Quach, Sean S. Kang
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Patent number: 9269590Abstract: Embodiments of the present invention pertain to methods of forming more symmetric spacers which may be used for self-aligned multi-patterning processes. A conformal spacer layer of spacer material is formed over mandrels patterned near the optical resolution of a photolithography system using a high-resolution photomask. A carbon-containing layer is further formed over the conformal spacer layer. The carbon-containing layer is anisotropically etched to expose the high points of the conformal spacer layer while retaining carbon side panels. The conformal spacer layer may then be etched to form spacers without the traditional skewing of the profile towards one side or the other.Type: GrantFiled: April 7, 2014Date of Patent: February 23, 2016Assignee: Applied Materials, Inc.Inventors: Olivier Luere, Sean S. Kang, Srinivas D. Nemani
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Publication number: 20150287612Abstract: Embodiments of the present invention pertain to methods of forming more symmetric spacers which may be used for self-aligned multi-patterning processes. A conformal spacer layer of spacer material is formed over mandrels patterned near the optical resolution of a photolithography system using a high-resolution photomask. A carbon-containing layer is further formed over the conformal spacer layer. The carbon-containing layer is anisotropically etched to expose the high points of the conformal spacer layer while retaining carbon side panels. The conformal spacer layer may then be etched to form spacers without the traditional skewing of the profile towards one side or the other.Type: ApplicationFiled: April 7, 2014Publication date: October 8, 2015Inventors: Olivier Luere, Sean S. Kang, Srinivas D. Nemani
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Publication number: 20150214066Abstract: Embodiments of the technology include a semiconductor patterning method. The method may include forming a layer of masking material on regions of dielectric material above a semiconductor substrate. The method may include forming a trench through the masking material. This transformation may expose at least a portion of the dielectric material. The method may include forming a protective layer over the exposed portion of the dielectric material. The method may involve removing the masking material from the semiconductor substrate.Type: ApplicationFiled: January 27, 2014Publication date: July 30, 2015Applicant: Applied Materials, Inc.Inventors: Olivier Luere, Srinivas D. Nemani, Sean S. Kang
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Publication number: 20150200042Abstract: A portion of the ultra-low k dielectric layer over a substrate is modified using a downstream plasma comprising a first chemistry. The modified portion of the ultra-low k dielectric layer is etched using the downstream plasma comprising a second chemistry. The downstream plasma is generated using a remote plasma source.Type: ApplicationFiled: January 10, 2014Publication date: July 16, 2015Applicant: Applied Materials, Inc.Inventors: Mang Mang Ling, Sean S. Kang, Jeremiah T P Pender, Srinivas D. Nemani, Bradley J. Howard
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Patent number: 9006106Abstract: Methods of removing metal hardmasks in the presence of ultra low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film includes forming a pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. The method also includes etching, using the metal nitride hardmask layer as a mask, the pattern at least partially into the low-k dielectric film, the etching involving using a plasma etch based on SiFx. The etching also involves forming an SiOx passivation layer at least on sidewalls of the low-k dielectric film formed during the etching. The method also includes removing the metal nitride hardmask layer by a dry etch process, where the SiOx passivation layer protects the low-k dielectric film during the removing.Type: GrantFiled: May 8, 2013Date of Patent: April 14, 2015Assignee: Applied Materials, Inc.Inventors: Chia-Ling Kao, Kwang-soo Kim, Sean S. Kang, Srinivas D. Nemani
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Patent number: 8992792Abstract: Methods of fabricating ultra low-k dielectric self-aligned vias are described. In an example, a method of forming a self-aligned via (SAV) in a low-k dielectric film includes forming a trench pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. A via pattern is formed in a masking layer formed above the metal nitride hardmask layer. The via pattern is etched at least partially into the low-k dielectric film, the etching comprising using a plasma etch using a chemistry based on CF4, H2, and a diluent inert gas composition.Type: GrantFiled: December 21, 2012Date of Patent: March 31, 2015Assignee: Applied Materials, Inc.Inventors: Chih-Yang Chang, Sean S. Kang, Chia-Ling Kao, Nikolaos Bekiaris
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Patent number: 8987139Abstract: Methods of patterning low-k dielectric films are described. In an example, In an embodiment, a method of patterning a low-k dielectric film involves forming and patterning a metal nitride mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves passivating the metal nitride mask layer by treating with a plasma based on O2/N2/SixFy. The method also involves etching a portion of the low-k dielectric layer.Type: GrantFiled: January 21, 2014Date of Patent: March 24, 2015Assignee: Applied Materials, Inc.Inventors: Chia-Ling Kao, Sean S. Kang, Srinivas D. Nemani
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Publication number: 20150079798Abstract: Methods for etching an etching stop layer disposed on the substrate using a cyclical etching process are provided. In one embodiment, a method for etching an etching stop layer includes performing a treatment process on the substrate having a silicon nitride layer disposed thereon by supplying a treatment gas mixture into the processing chamber to treat the silicon nitride layer, and performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process etches the treated silicon nitride layer.Type: ApplicationFiled: September 17, 2013Publication date: March 19, 2015Inventors: Mang-Mang LING, Sean S. KANG, Jeremiah T. P. PENDER, Srinivas D. NEMANI, Bradley HOWARD
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Patent number: 8980758Abstract: Methods for etching an etching stop layer disposed on the substrate using a cyclical etching process are provided. In one embodiment, a method for etching an etching stop layer includes performing a treatment process on the substrate having a silicon nitride layer disposed thereon by supplying a treatment gas mixture into the processing chamber to treat the silicon nitride layer, and performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process etches the treated silicon nitride layer.Type: GrantFiled: September 17, 2013Date of Patent: March 17, 2015Assignee: Applied Materials, Inc.Inventors: Mang-Mang Ling, Sean S. Kang, Jeremiah T. P. Pender, Srinivas D. Nemani, Bradley Howard
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Publication number: 20150064921Abstract: Methods for etching a material layer disposed on the substrate using a low temperature etching process along with a subsequent low temperature plasma annealing process are provided. In one embodiment, a method for etching a material layer disposed on a substrate includes transferring a substrate having a material layer disposed thereon into an etching processing chamber, supplying an etching gas mixture into the processing chamber, remotely generating a plasma in the etching gas mixture to etch the material layer disposed on the substrate, and plasma annealing the material layer at a substrate temperature less than 100 degrees Celsius.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Inventors: Srinivas D. NEMANI, Sean S. KANG, Jeremiah T. P. PENDER, Chia-Ling KAO, Sergey G. BELOSTOTSKIY, Lina ZHU
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Publication number: 20150056814Abstract: Methods for etching a material layer disposed on the substrate using a combination of a main etching step and a cyclical etching process are provided. The method includes performing a main etching process in a processing chamber to an oxide layer, forming a feature with a first predetermined depth in the oxide layer, performing a treatment process on the substrate by supplying a treatment gas mixture into the processing chamber to treat the etched feature in the oxide layer, performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process further etches the feature to a second predetermined depth, and performing a transition process on the etched substrate by supplying a transition gas mixture into the processing chamber.Type: ApplicationFiled: October 21, 2013Publication date: February 26, 2015Inventors: Mang-Mang LING, Jungmin KO, Sean S. KANG, Jeremiah T. PENDER, Srinivas D. NEMANI, Bradley HOWARD
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Publication number: 20140357083Abstract: Embodiments of methods and an apparatus for utilizing a directed self-assembly (DSA) process on block copolymers (BCPs) to form a defect-free photoresist layer for feature transfer onto a substrate are provided. In one embodiment, a method for performing a dry development process includes transferring a substrate having a layer of block copolymers disposed thereon into an etching processing chamber, wherein at least a first type and a second type of polymers comprising the block copolymers are aggregated into a first group of regions and a second group of regions on the substrate, supplying an etching gas mixture including at least a carbon containing gas into the etching processing chamber, and predominately etching the second type of the polymers disposed on the second groups of regions on the substrate in the presence of the etching gas mixture.Type: ApplicationFiled: May 21, 2014Publication date: December 4, 2014Applicant: APPLIED MATERIALS, INC.Inventors: Mang-Mang LING, Lina ZHU, Nancy FUNG, Kwang-Soo KIM, Sean S. KANG, Srinivas D. NEMANI