Patents by Inventor Sean Stephens
Sean Stephens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250147897Abstract: Systems, methods and apparatuses of fine grain data migration in using memory as a service (MaaS) are described. For example, a memory status map can be used to identify the cache availability of sub-regions (e.g., cache lines) of a borrowed memory region (e.g., a borrowed remote memory page). Before accessing a virtual memory address in a sub-region, the memory status map is checked. If the sub-region has cache availability in the local memory, the memory management unit uses a physical memory address converted from the virtual memory address to make memory access. Otherwise, the sub-region is cached from the borrowed memory region to the local memory, before the physical memory address is used.Type: ApplicationFiled: January 10, 2025Publication date: May 8, 2025Inventors: Dmitri Yudanov, Ameen D. Akel, Samuel E. Bradshaw, Kenneth Marion Curewitz, Sean Stephen Eilert
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Patent number: 12271262Abstract: Systems, methods, and apparatus related to data recovery in memory devices. In one approach, a memory device encodes stored data. The memory device reads a codeword from a storage media and determines that a number errors in the codeword exceeds an error correction capability of the memory device. The errors are due, for example, to one or more stuck bits. In response to this determination, one or more data patterns are written to the storage media at the same address from which the codeword is read. The data patterns are read to identify bit locations of the stuck bits. The identified locations are used to correct bit errors of the read codeword that correspond to the identified locations. The corrected code word is sent to a host device (e.g., which requested data from the memory device using a read command).Type: GrantFiled: July 6, 2022Date of Patent: April 8, 2025Assignee: Micron Technology, Inc.Inventors: Richard Edward Fackenthal, Sean Stephen Eilert
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Publication number: 20250094815Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for generating and providing customized content labels as elements for seamless integration within a graphical interface. For instance, the disclosed systems provide generative options utilizing contextual data to more effectively incorporate a content label (textual and/or visual) based on the surrounding graphical elements, the functionality of the label within the interface, and the purpose of the label or interface. In this way, the disclosed systems generate contextual labels with appropriate textual content and that are appropriately sized, styled, and positioned based on their relevance within the context of the graphical interface.Type: ApplicationFiled: September 19, 2023Publication date: March 20, 2025Inventors: Tony Xu, Sean Stephens
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Patent number: 12248412Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN) as well as different versions of a feature dictionary. In the system, encoded inputs for the ANN can be decoded by the feature dictionary, which allows for encoded input to be sent to a master version of the ANN over a network instead of an original version of the input which usually includes more data than the encoded input. Thus, by using the feature dictionary for training of a master ANN there can be reduction of data transmission.Type: GrantFiled: June 15, 2022Date of Patent: March 11, 2025Assignee: Micron Technology, Inc.Inventors: Kenneth Marion Curewitz, Ameen D. Akel, Hongyu Wang, Sean Stephen Eilert
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Publication number: 20240427708Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.Type: ApplicationFiled: September 9, 2024Publication date: December 26, 2024Inventors: Samuel E. Bradshaw, Shivam Swami, Sean Stephen Eilert, Justin M. Eno, Ameen D. Akel
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Publication number: 20240403225Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.Type: ApplicationFiled: August 16, 2024Publication date: December 5, 2024Inventors: Samuel E. Bradshaw, Justin M. Eno, Sean Stephen Eilert, Shivasankar Gunasekaran, Hongyu Wang, Shivam Swami
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Publication number: 20240370208Abstract: A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.Type: ApplicationFiled: July 19, 2024Publication date: November 7, 2024Inventors: Kenneth Marion Curewitz, Shivam Swami, Samuel E. Bradshaw, Justin M. Eno, Ameen D. Akel, Sean Stephen Eilert
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Publication number: 20240345957Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.Type: ApplicationFiled: June 21, 2024Publication date: October 17, 2024Inventors: Kenneth Marion Curewitz, Ameen D. Akel, Samuel E. Bradshaw, Sean Stephen Eilert, Dmitri Yudanov
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Patent number: 12086078Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.Type: GrantFiled: August 15, 2022Date of Patent: September 10, 2024Assignee: Micron Technology, Inc.Inventors: Samuel E. Bradshaw, Shivam Swami, Sean Stephen Eilert, Justin M. Eno, Ameen D. Akel
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Patent number: 12066951Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.Type: GrantFiled: October 12, 2022Date of Patent: August 20, 2024Assignee: Micron Technology, Inc.Inventors: Samuel E. Bradshaw, Justin M. Eno, Sean Stephen Eilert, Shivasankar Gunasekaran, Hongyu Wang, Shivam Swami
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Publication number: 20240248852Abstract: Systems, methods and apparatuses of distributed computing based on memory as a service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.Type: ApplicationFiled: April 1, 2024Publication date: July 25, 2024Inventors: Ameen D. Akel, Samuel E. Bradshaw, Kenneth Marion Curewitz, Sean Stephen Eilert, Dmitri Yudanov
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Patent number: 12019549Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.Type: GrantFiled: January 12, 2022Date of Patent: June 25, 2024Assignee: Micron Technology, Inc.Inventors: Kenneth Marion Curewitz, Ameen D. Akel, Samuel E. Bradshaw, Sean Stephen Eilert, Dmitri Yudanov
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Publication number: 20240152464Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).Type: ApplicationFiled: January 5, 2024Publication date: May 9, 2024Inventors: Kenneth Marion Curewitz, Sean Stephen Eilert, Hongyu Wang, Samuel E. Bradshaw, Shivasankar Gunasekaran, Justin M. Eno, Shivam Swami
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Patent number: 11954042Abstract: Systems, methods and apparatuses of distributed computing based on memory as a service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.Type: GrantFiled: September 13, 2022Date of Patent: April 9, 2024Assignee: Micron Technology, Inc.Inventors: Ameen D. Akel, Samuel E. Bradshaw, Kenneth Marion Curewitz, Sean Stephen Eilert, Dmitri Yudanov
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Patent number: 11755884Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, changes to local versions of the ANN can be combined with a master version of the ANN. In the system, a first device can include memory that can store the master version, a second device can include memory that can store a local version of the ANN, and there can be many devices that store local versions of the ANN. The second device (or any other device of the system hosting a local version) can include a processor that can train the local version, and a transceiver that can transmit changes to the local version generated from the training. The first device can include a transceiver that can receive the changes to a local version, and a processing device that can combine the received changes with the master version.Type: GrantFiled: August 20, 2019Date of Patent: September 12, 2023Assignee: Micron Technology, Inc.Inventors: Sean Stephen Eilert, Shivasankar Gunasekaran, Ameen D. Akel, Kenneth Marion Curewitz, Hongyu Wang
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Patent number: 11693593Abstract: Various embodiments enable versioning of data stored on a memory device, where the versioning allows the memory device to maintain different versions of data within a set of physical memory locations (e.g., a row) of the memory device. In particular, some embodiments provide for a memory device or a memory sub-system that uses versioning of stored data to facilitate a rollback operation/behavior, a checkpoint operation/behavior, or both. Additionally, some embodiments provide for a transactional memory device or a transactional memory sub-system that uses versioning of stored data to enable rollback of a memory transaction, commitment of a memory transaction, or handling of a read or write command associated with respect to a memory transaction.Type: GrantFiled: October 28, 2020Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: David Andrew Roberts, Sean Stephen Eilert
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Patent number: 11657002Abstract: Systems, methods and apparatuses to accelerate accessing of borrowed memory over network connection are described. For example, a memory management unit (MMU) of a computing device can be configured to be connected both to the random access memory over a memory bus and to a computer network via a communication device. The computing device can borrow an amount of memory from a remote device over a network connection using the communication device; and applications running in the computing device can use virtual memory addresses mapped to the borrowed memory. When a virtual address mapped to the borrowed memory is used, the MMU translates the virtual address into a physical address and instruct the communication device to access the borrowed memory.Type: GrantFiled: July 14, 2021Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Samuel E. Bradshaw, Ameen D. Akel, Kenneth Marion Curewitz, Sean Stephen Eilert, Dmitri Yudanov
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Patent number: 11636334Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, inputs for the ANN can be obfuscated for centralized training of a master version of the ANN at a first computing device. A second computing device in the system includes memory that stores a local version of the ANN and user data for inputting into the local version. The second computing device includes a processor that extracts features from the user data and obfuscates the extracted features to generate obfuscated user data. The second device includes a transceiver that transmits the obfuscated user data. The first computing device includes a memory that stores the master version of the ANN, a transceiver that receives obfuscated user data transmitted from the second computing device, and a processor that trains the master version based on the received obfuscated user data using machine learning.Type: GrantFiled: August 20, 2019Date of Patent: April 25, 2023Assignee: Micron Technology, Inc.Inventors: Samuel E. Bradshaw, Shivasankar Gunasekaran, Sean Stephen Eilert, Ameen D. Akel, Kenneth Marion Curewitz
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Publication number: 20230033549Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.Type: ApplicationFiled: October 12, 2022Publication date: February 2, 2023Inventors: Samuel E. Bradshaw, Justin M. Eno, Sean Stephen Eilert, Shivasankar Gunasekaran, Hongyu Wang, Shivam Swami
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Patent number: 11562060Abstract: A method, system and apparatus are disclosed. A device includes processing circuitry that includes a processor and a memory, where the memory is configured to store a logical container including a plurality of encrypted data portions and a plurality of executable code portions. Each encrypted data portion and executable code portion is separately encrypted with a different encryption key and associated with a user. The processing circuitry receives, from a software application operating in another device, a first request associated with at least one encrypted data portion and one executable code portion of the logical container. The first request includes an encryption token associated with the software application. In response to the first request, the processing circuitry triggers a verification code portion to determine whether the first request is authorized and performs at least one operation to fulfill the first request in response to determining the request is authorized.Type: GrantFiled: September 21, 2021Date of Patent: January 24, 2023Assignee: Conveyance Media Group LLCInventors: Sean Stephens, George E. Manges, William Browning