Abstract: A phased-array receiver that may be effectively implemented on a silicon substrate. A receiver includes multiple radio frequency (RF) front-ends, each configured to receive a signal with a given delay relative to the others such that the gain of the received signal is highest in a given direction. The receiver also includes a power combination network configured to accept an RF signal from each of the RF front-ends and to pass a combined RF signal to a down-conversion element, where the power distribution network includes a combination of active and passive components. Each RF front-end includes a phase shifter configured to delay the signal in accordance with the given direction and a variable amplifier configured to adjust the gain of the signal.

Abstract: A phased-array receiver that may be effectively implemented on a silicon substrate. A receiver includes multiple radio frequency (RF) front-ends, each configured to receive a signal with a given delay relative to the others such that the gain of the received signal is highest in a given direction. The receiver also includes a power combination network configured to accept an RF signal from each of the RF front-ends and to pass a combined RF signal to a down-conversion element, where the power distribution network includes a combination of active and passive components. Each RF front-end includes a phase shifter configured to delay the signal in accordance with the given direction and a variable amplifier configured to adjust the gain of the signal.

Abstract: A phased-array transmitter and receiver that may be effectively implemented on a silicon substrate. The transmitter distributes to front-ends, and the receiver combines signals from front-ends, using a power distribution/combination tree that employs both passive and active elements. By monitoring the power inputs and outputs, a digital control is able to rapidly provide phase and gain correction information to the front-ends. Such a transmitter/receiver includes a plurality of radio frequency (RF) front-ends and a power splitting/combining network that includes active and passive components configured to distribute signals to/from the front-ends.

Abstract: A system-on-chip (SOC) transceiver is provided. The transceiver is configured to operate in excess of 100 GHz and comprising the following components. A quadrature oscillator is configured to generate a fundamental frequency and a second harmonic frequency and comprises at least a pair of high frequency outputs at said second harmonic frequency. At least the second harmonic frequency exceeds 100 GHz. A transmission output is coupled to one of the high frequency outputs for transmitting an output signal at the second harmonic frequency. A transmission signal transformer is coupled to the other one of the high frequency outputs and configured to generate a differential oscillator signal at the second harmonic frequency. A radio frequency input receives radio frequency signals at the transceiver from an antenna. A radio frequency signal transformer coupled to the radio frequency input is configured to generate a differential radio frequency signal at the radio frequency.

Abstract: A phased-array transmitter and receiver that may be effectively implemented on a silicon substrate. The transmitter distributes to front-ends, and the receiver combines signals from front-ends, using a power distribution/combination tree that employs both passive and active elements. By monitoring the power inputs and outputs, a digital control is able to rapidly provide phase and gain correction information to the front-ends. Such a transmitter/receiver includes a plurality of radio frequency (RF) front-ends and a power splitting/combining network that includes active and passive components configured to distribute signals to/from the front-ends.

Abstract: A direct conversion radio frequency (RF) transceiver integrated circuit (IC) is provided. The IC includes a local oscillator block, a receiver block, and a transmitter block disposed on a single silicon-based integrated circuit. Each of such blocks are connected to a ground plane that includes a metal located adjacent to each of such blocks, air gaps located between each section of the metal adjacent to such blocks, each section of the metal being connected to the adjacent section of metal in the group plane at a location on the edge of the ground plan corresponding to a point substantially equidistant from the two sections of metal. A system and method is provided for implementing a direct conversion integrated circuit architecture. A clock distribution system is provided, as well as a method for radio detection and ranging (RADAR) using a Doppler RADAR transceiver system in the W-band. A method for noise isolation between blocks of an integrated circuit is also provided.

Abstract: A system-on-chip (SOC) transceiver is provided. The transceiver is configured to operate in excess of 100 GHz and comprising the following components. A quadrature oscillator is configured to generate a fundamental frequency and a second harmonic frequency and comprises at least a pair of high frequency outputs at said second harmonic frequency. At least the second harmonic frequency exceeds 100 GHz. A transmission output is coupled to one of the high frequency outputs for transmitting an output signal at the second harmonic frequency. A transmission signal transformer is coupled to the other one of the high frequency outputs and configured to generate a differential oscillator signal at the second harmonic frequency. A radio frequency input receives radio frequency signals at the transceiver from an antenna. A radio frequency signal transformer coupled to the radio frequency input is configured to generate a differential radio frequency signal at the radio frequency.