Abstract: Methods and apparatus for providing page migration of pages among tiered memories identify frequently accessed memory pages in each memory tier and generate page hotness ranking information indicating how frequently memory pages are being accessed. Methods and apparatus provide the page hotness ranking information to an operating system or hypervisor depending on which is used in the system, the operating system or hypervisor issues a page move command to a hardware data mover, based on the page hotness ranking information and the hardware data mover moves a memory page to a different memory tier in response to the page move command from the operating system.

Abstract: A system and method for finding the sources of increased interrupt latencies. An interrupt controller includes monitoring logic for measuring and storing latencies for servicing interrupt requests. The interrupt controller determines a measured latency is greater than an associated threshold and in response sends an indication of a long latency. The interrupt controller may send the indication to firmware, a device driver, or other software. The interrupt controller stores associated information with the measured latency for debug purposes. Additionally, the monitoring logic may perform statistical analysis in place of, or in addition to, software.

Abstract: A method of managing cache memory includes assigning a caching priority designator to an address that addresses information stored in a memory system. The information is stored in a cacheline of a first level of cache memory in the memory system. The cacheline is evicted from the first level of cache memory. A second level in the memory system to which to write back the information is determined based at least in part on the caching priority designator. The information is written back to the second level.

Abstract: A system and method for finding the sources of increased interrupt latencies. An interrupt controller includes monitoring logic for measuring and storing latencies for servicing interrupt requests. The interrupt controller determines a measured latency is greater than an associated threshold and in response sends an indication of a long latency. The interrupt controller may send the indication to firmware, a device driver, or other software. The interrupt controller stores associated information with the measured latency for debug purposes. Additionally, the monitoring logic may perform statistical analysis in place of, or in addition to, software.

Abstract: A method of controlling memory read behavior in PCI devices includes connecting a master PCI device to a PCI bus. The master PCI device is constructed and arranged to issue a Memory Read Line or a Memory Read Multiple initial command. A target PCI bridge device is connected to the PCI bus. The target PCI bridge device is constructed and arranged to prefetch data from host memory on behalf of the master PCI device and to store the prefetched data. A data transfer transaction is established between the master PCI device and the target PCI bridge device and prefetched data is stored at the target PCI bridge device. A bit is selectively preset in at least one of the PCI devices such that if a disconnect of the transaction occurs, the target PCI bridge device recognizes a subsequent request as a continuation of the initial request and sends prefetched data to the master PCI device.