Patents by Inventor Sean Tristram Ellis

Sean Tristram Ellis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9965876
    Abstract: A graphics processing pipeline determines whether respective graphics processing operations, such as respective blends, respective depth tests, etc., to be performed at a stage of the graphics processing pipeline would produce the same result for each sampling point of a set of plural sampling points represented by a fragment being processed by the graphics processing pipeline. If it is determined that respective graphics processing operations would produce the same result for each of the sampling points, then only a single instance of the graphics processing operation is performed and the result of that graphics processing operation is associated with each of the sampling points. The number of instances of the graphics processing operations needed to process the set of plural sampling points which the fragment represents is reduced in comparison to conventional multisampling graphics processing techniques which perform graphics processing operations for fragments on a “per sample” basis.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: May 8, 2018
    Assignee: Arm Limited
    Inventors: Andreas Engh Halstvedt, Sean Tristram Ellis, Jorn Nystad, Sandeep Kakarlapudi
  • Patent number: 9916675
    Abstract: In a tile-based graphics processing system, when a tile for a render output is to be generated, the fragment data storage requirements for each fragment to be generated for the tile is determined 51, and a color and/or depth buffer in the tile buffer is allocated for use by the fragments for the tile based on the determination 57. The graphics processing pipeline then, when generating rendered fragment data for the tile, stores the rendered fragment data in the color buffer and/or depth buffer of the tile buffer allocated to the fragments for the tile 58.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: March 13, 2018
    Assignee: Arm Limited
    Inventors: Edward Charles Plowman, Sean Tristram Ellis
  • Patent number: 9837048
    Abstract: A data processing system 30 includes a CPU 33, a GPU 34, a video processing engine (video engine) 35, a display controller 36 (or an image processing engine) and a memory controller 313 all having access to off-chip memory 314. A frame to be displayed is generated by, for example, being appropriately rendered by the GPU 34 or video engine 35. The display controller 36 (or the image processing engine) then performs display modifications, such as luminance compensation, on the frame to provide an output frame for display. The display controller 36 (or the image processing engine) also provides display modification information (such as determined luminance compensation parameters) to the GPU 33 and video engine 34. The display modification information is then used to modify the data that is generated for a frame to be displayed.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: December 5, 2017
    Assignee: Arm Limited
    Inventors: Daren Croxford, Sean Tristram Ellis
  • Patent number: 9741089
    Abstract: A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: August 22, 2017
    Assignee: ARM LIMITED
    Inventors: Anders Lassen, Jorn Nystad, Alexis Mather, Sean Tristram Ellis
  • Patent number: 9672162
    Abstract: A data processing system includes a host processor and a graphics processing unit operable to process data under the control of an operating system executing on the host processor. The graphics processing unit can be switched between a normal mode of operation in which the it has read and write access to data that is stored in non-protected memory regions 9 but no or write-only access to any protected memory regions 8, and a protected mode of operation in which it has read and write access to data that is stored in protected memory regions 8 but only has read-only access to any non-protected memory regions 9. The data processing system further comprises a mechanism for switching the graphics processing unit from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: June 6, 2017
    Assignee: ARM LIMITED
    Inventors: Hakan Persson, Sean Tristram Ellis
  • Patent number: 9514563
    Abstract: When processing a set of tiles to generate an output in a tile based graphics processing pipeline, the pipeline, for one or more tiles of the set of tiles, renders one or more render targets containing data to be used in a processing operation (602), and stores the render targets in the tile buffer (604). It also stores some but not all of the sampling position values for a render target or targets for use when processing an adjacent tile of the set of tiles (606). It then performs a processing operation for the tile using the stored render target or targets (608) and one or more stored sampling position values from another, adjacent tile of the set of tiles (610), to generate an output for the tile (612).
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 6, 2016
    Assignee: ARM LIMITED
    Inventors: Sean Tristram Ellis, Jorn Nystad, Andreas Engh-Halstvedt
  • Patent number: 9489344
    Abstract: A data processor of a processing system, such as a graphics processing system, converts an input data value into an output data value by approximating a function which maps input values to output values. The data processor approximates the function using first and second predetermined ranges of values which are quantized into plural corresponding pairs of range sections, a predetermined gradient for each pair of range sections, and predetermined section end values for each pair of range sections. By using these predetermined parameters, the approximation of the function can be implemented efficiently by the data processor of the processing system.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: November 8, 2016
    Assignee: ARM LIMITED
    Inventors: Jorn Nystad, Sean Tristram Ellis
  • Patent number: 9472008
    Abstract: A graphics processing apparatus performs tile based compositing operations. Tile metadata includes flag data, such as transparency and/or intensity flag data, indicating whether a given input graphics tile makes less than a predetermined first threshold level of contribution or more than a second predetermined threshold level of contribution to a corresponding output graphics tile. For example, if an input graphics tile is transparent, then its reading from a memory and/or subsequent processing may be suppressed. If a given input graphics tile is opaque, then underlying input graphics tiles that are obscured may have their reading and/or further processing suppressed.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: October 18, 2016
    Assignee: ARM Limited
    Inventors: Daren Croxford, Thomas James Cooksey, Sean Tristram Ellis
  • Patent number: 9195426
    Abstract: In a data processing system, an output surface, such as frame to be displayed, is generated as a plurality of respective regions with each respective region of the output surface being generated from a respective region or regions of one or more input surfaces. When a new version of the output surface is to be generated 80, for each region of the output surface it is determined which region or regions of the input surface or surfaces contribute to the region of the output surface 84 and then checked whether the contributing region or regions of the input surface or surfaces have changed since the previous version of the output surface region was generated 85. If there has been a change in the contributing region or regions of the input surface or surfaces since the previous version of the region in the output surface was generated 86, the region of the output surface is regenerated 87.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: November 24, 2015
    Assignee: ARM Limited
    Inventors: Daren Croxford, Tom Cooksey, Lars Ericsson, Sean Tristram Ellis
  • Patent number: 9177415
    Abstract: When encoding an array of texture data elements to be used in a graphics processing system, the array of texture data elements is divided into a plurality of non-rectangular sub-sets of texture data elements, and each non-rectangular sub-set of texture data elements that the texture has been divided into is then encoded to generate an encoded texture data block representing that non-rectangular sub-set of the texture data elements, to thereby provide a set of encoded texture data blocks representing the texture.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 3, 2015
    Assignee: ARM LIMITED
    Inventor: Sean Tristram Ellis
  • Publication number: 20150310791
    Abstract: A data processing system 30 includes a CPU 33, a GPU 34, a video processing engine (video engine) 35, a display controller 36 (or an image processing engine) and a memory controller 313 all having access to off-chip memory 314. A frame to be displayed is generated by, for example, being appropriately rendered by the GPU 34 or video engine 35. The display controller 36 (or the image processing engine) then performs display modifications, such as luminance compensation, on the frame to provide an output frame for display. The display controller 36 (or the image processing engine) also provides display modification information (such as determined luminance compensation parameters) to the GPU 33 and video engine 34. The display modification information is then used to modify the data that is generated for a frame to be displayed.
    Type: Application
    Filed: April 9, 2015
    Publication date: October 29, 2015
    Applicant: ARM LIMITED
    Inventors: Daren Croxford, Sean Tristram Ellis
  • Patent number: 9128531
    Abstract: A single instruction multiple data processing pipeline 12 for processing floating point operands includes shared special case handling circuitry 34 for performing any operand dependent special case processing operations. The operand dependent special case processing operations result from special case conditions such as operands that are denormal, an infinity, a not-a-number and a floating point number requiring format conversion. The pipeline 12 may in some embodiments be stalled while the operands requiring special case processing are serially shifted to and from the shared special case handling circuitry 34. In other embodiments the instruction in which the special case condition for an operand arose may be recirculated through the pipeline with permutation circuitry 86, 94 being used to swap the operands between lanes in order to place the operand(s) requiring special case processing operations into the lane containing the shared special case handling circuitry 98.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: September 8, 2015
    Assignee: ARM Limited
    Inventors: Sean Tristram Ellis, Simon Alex Charles, Andrew Burdass
  • Publication number: 20150084983
    Abstract: In a data processing system, an output surface, such as frame to be displayed, is generated as a plurality of respective regions with each respective region of the output surface being generated from a respective region or regions of one or more input surfaces. When a new version of the output surface is to be generated 80, for each region of the output surface it is determined which region or regions of the input surface or surfaces contribute to the region of the output surface 84 and then checked whether the contributing region or regions of the input surface or surfaces have changed since the previous version of the output surface region was generated 85. If there has been a change in the contributing region or regions of the input surface or surfaces since the previous version of the region in the output surface was generated 86, the region of the output surface is regenerated 87.
    Type: Application
    Filed: April 17, 2014
    Publication date: March 26, 2015
    Applicant: ARM LIMITED
    Inventors: Daren CROXFORD, Tom Cooksey, Lars Ericsson, Sean Tristram Ellis
  • Publication number: 20150062154
    Abstract: When processing a set of tiles to generate an output in a tile based graphics processing pipeline, the pipeline, for one or more tiles of the set of tiles, renders one or more render targets containing data to be used in a processing operation (602), and stores the render targets in the tile buffer (604). It also stores some but not all of the sampling position values for a render target or targets for use when processing an adjacent tile of the set of tiles (606). It then performs a processing operation for the tile using the stored render target or targets (608) and one or more stored sampling position values from another, adjacent tile of the set of tiles (610), to generate an output for the tile (612).
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Inventors: Sean Tristram Ellis, Jorn Nystad, Andreas Engh-Halstvedt
  • Publication number: 20150052325
    Abstract: A data processing system includes a host processor and a graphics processing unit operable to process data under the control of an operating system executing on the host processor. The graphics processing unit can be switched between a normal mode of operation in which the it has read and write access to data that is stored in non-protected memory regions 9 but no or write-only access to any protected memory regions 8, and a protected mode of operation in which it has read and write access to data that is stored in protected memory regions 8 but only has read-only access to any non-protected memory regions 9. The data processing system further comprises a mechanism for switching the graphics processing unit from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Inventors: Hakan Persson, Sean Tristram Ellis
  • Publication number: 20150049118
    Abstract: A graphics processing apparatus (2) performs tile based compositing operations. Tile metadata includes flag data (tfd), such as transparency and/or intensity flag data, indicating whether a given input graphics tile make less than a predetermined first threshold level of contribution or more than a second predetermined threshold level of contribution to a corresponding output graphics tile. For example, if an input graphics tile is transparent, then its reading from a memory (6) and/or subsequent processing may be suppressed. If a given input graphics tile is opaque, then any underlying input graphics tiles were are obscured may have their reading and/or further processing suppressed.
    Type: Application
    Filed: June 19, 2014
    Publication date: February 19, 2015
    Inventors: Daren CROXFORD, Thomas James Cooksey, Sean Tristram Ellis
  • Patent number: 8959304
    Abstract: A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of des
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: February 17, 2015
    Assignee: ARM Limited
    Inventors: Dominic Hugo Symes, Ola Hugosson, Donald Felton, Sean Tristram Ellis
  • Publication number: 20150002524
    Abstract: A data processor of a processing system, such as a graphics processing system, converts an input data value into an output data value by approximating a function which maps input values to output values. The data processor approximates the function using first and second predetermined ranges of values which are quantised into plural corresponding pairs of range sections, a predetermined gradient for each pair of range sections, and predetermined section end values for each pair of range sections. By using these predetermined parameters, the approximation of the function can be implemented efficiently by the data processor of the processing system.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventors: Jorn Nystad, Sean Tristram Ellis
  • Publication number: 20140368521
    Abstract: A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.
    Type: Application
    Filed: May 2, 2014
    Publication date: December 18, 2014
    Applicant: ARM Limited
    Inventors: Anders Lassen, Jorn Nystad, Alexis Mather, Sean Tristram Ellis
  • Publication number: 20140354671
    Abstract: In a tile-based graphics processing system, when a tile for a render output is to be generated, the fragment data storage requirements for each fragment to be generated for the tile is determined 51, and a colour and/or depth buffer in the tile buffer is allocated for use by the fragments for the tile based on the determination 57. The graphics processing pipeline then, when generating rendered fragment data for the tile, stores the rendered fragment data in the colour buffer and/or depth buffer of the tile buffer allocated to the fragments for the tile 58.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Inventors: Edward Charles Plowman, Sean Tristram Ellis