Abstract: A fast Fourier transform (FFT) circuit with an integrated half-bin offset for performing both an FFT and a half-bin offset on an input signal. The FFT circuit is configured to receive input samples of the input signal and generate output signals via a plurality of butterfly circuits and one or more twiddle stage multiplier circuits of the FFT circuit. One or more of the butterfly circuits are configured to implement a first portion of both the half-bin offset and the FFT by integrating a first set of computations for both the half-bin offset and the FFT within the one or more of the plurality of butterfly circuits. At least one of the one or more twiddle stage multiplier circuits is configured to implement a second portion of both the half-bin offset and the FFT by integrating a second set of computations of both the half-bin offset and the FFT within the twiddle stage multiplier circuit.