Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.

Abstract: Interconnect structures and methods of forming interconnect structures. An opening is formed that penetrates from a top surface of a dielectric layer into the dielectric layer. A first conductor layer is conformally deposited with a uniform thickness on the dielectric layer surrounding the first opening. A second conductor layer is formed in a space inside the first opening that is interior of the first conductor layer. The first conductor layer and the second conductor layer collectively define a hybrid feature that is embedded in the dielectric layer.

Abstract: Methods for forming interconnects that include cobalt. An interconnect opening is formed in a dielectric layer that penetrates from a top surface of the dielectric layer into the dielectric layer. A first cobalt layer is formed at a bottom of the interconnect opening and partially fills the interconnect opening. A second cobalt layer is selectively deposited on the first cobalt layer and grows upwardly from the first cobalt layer at the bottom of the interconnect opening.

Abstract: One illustrative method disclosed includes, among other things, forming a gate contact opening in a layer of insulating material, performing at least one etching process through the gate contact opening to remove a gate cap layer and to expose the gate structure, selectively growing a metal material that is conductively coupled to an upper surface of the gate structure such that the grown metal material contacts all of the sidewalls of the gate contact opening and an air space is formed between a bottom of the grown metal material and a conductive source/drain structure, and forming one or more conductive materials in the gate contact opening above the grown metal material.

Abstract: A method of fabricating amorphous metal interconnections includes forming an amorphous metal layer over a base insulating layer on a semiconductor device using an amorphous metal having a non-crystalline structure. A portion of the amorphous metal layer is selectively removed to form a three dimensional pattern within a remaining portion of the amorphous metal layer. A fill insulating layer is disposed over the remaining portion of the amorphous metal layer and base insulating layer to fill the three dimensional pattern to form amorphous metal interconnects between semiconductor devices.

Abstract: One illustrative method disclosed includes, among other things, forming a gate contact opening in a layer of insulating material, performing at least one etching process through the gate contact opening to remove a gate cap layer and to expose the gate structure, selectively growing a metal material that is conductively coupled to an upper surface of the gate structure such that the grown metal material contacts all of the sidewalls of the gate contact opening and an air space is formed between a bottom of the grown metal material and a conductive source/drain structure, and forming one or more conductive materials in the gate contact opening above the grown metal material.

Abstract: Integrated circuits and methods for fabricating integrated circuits with self-aligned vias are disclosed. A method for fabricating an integrated circuit includes forming a first conductive interconnect line overlying a semiconductor substrate. The method forms an insulator cap defining a gap overlying the first conductive interconnect line. An upper interlayer dielectric material is deposited over the insulator cap and in the gap over the first conductive interconnect line. A via is etched through the upper interlayer dielectric material and into the gap to expose the first conductive interconnect line. The method deposits a conductive material into the via to form a conductive via in contact with the first conductive interconnect line.

Abstract: Integrated circuits and methods for fabricating integrated circuits with self-aligned vias are disclosed. A method for fabricating an integrated circuit includes forming a first conductive interconnect line overlying a semiconductor substrate. The method forms an insulator cap defining a gap overlying the first conductive interconnect line. An upper interlayer dielectric material is deposited over the insulator cap and in the gap over the first conductive interconnect line. A via is etched through the upper interlayer dielectric material and into the gap to expose the first conductive interconnect line. The method deposits a conductive material into the via to form a conductive via in contact with the first conductive interconnect line.

Abstract: Circuit structure fabrication methods are provided which include: patterning at least one opening within a dielectric layer disposed over a substrate structure; providing a liner material within the at least one opening of the dielectric layer; disposing a surfactant over at least a portion of the liner material; and depositing, using an electroless process, a conductive material over the liner material to form a conductive structure, and the disposed surfactant inhibits formation of a void within the conductive structure.

Abstract: Circuit structure fabrication methods are provided which include: patterning at least one opening within a dielectric layer disposed over a substrate structure; providing a liner material within the at least one opening of the dielectric layer; disposing a surfactant over at least a portion of the liner material; and depositing, using an electroless process, a conductive material over the liner material to form a conductive structure, and the disposed surfactant inhibits formation of a void within the conductive structure.

Abstract: A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.

Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.

Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.

Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.

Abstract: A process is provided for the removal of contaminants from a semiconductor device, for example, removing contaminants from pores of an ultra-low k film. In one aspect, a method includes: providing a dielectric layer with contaminant-containing pores and exposing the dielectric layer to a supercritical fluid. The supercritical fluid can dissolve and remove the contaminants. In another aspect, an intermediate semiconductor device structure is provided that contains a dielectric layer with contaminant-containing pores and a supercritical fluid within the pores. In another aspect, a semiconductor device structure with a dielectric layer containing uncontaminated pores is provided.

Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.

Abstract: A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.

Abstract: Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

Abstract: Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.