Abstract: A semiconductor device with a 7F2 cell structure. In one embodiment, a bit line pitch of about 2?{square root over (3)}F and a word line pitch of about 2F may be configured for the semiconductor device. In one embodiment, each of the active areas of the semiconductor device may be rotated around a corresponding center region to be offset from a corresponding bit line region. A plurality of imaginary equal lateral triangles may be formed by connecting center regions located on adjacent bit line regions and by connecting adjacent center regions located on the same bit line region. In this manner, the active areas for the semiconductor device can be arranged in a close compact pile mode within the cell plane, thereby achieving better cell area utilization. The semiconductor device may be a dynamic random access memory (DRAM).