Abstract: A depth-wise convolution acceleration device using an MAC array processor structure according to the present invention may include a data output unit, which receives a data of each row of the image from the data buffer and inputs the data into convolution operation blocks while shifting the data N?1 times according to the kernel size (N×N) and a weight output unit, which receives the kernel data from the kernel buffer and sequentially inputs a weight value constituting the kernel data to each of the row convolution operation blocks, and inputs the weight delaying by N clocks if the row increases as N rows.