Abstract: This disclosure describes example alarm notification systems that can enable a clinician to respond to an alarm notification received via a computing device, which may have more advanced functionality than a pager. The clinician device may be a mobile device, such as a cellphone or smartphone, tablet, laptop, personal digital assistant (PDA), or the like. The clinician device may communicate with a remote server to obtain patient data generated by a patient device at the point-of-care (such as a bedside device or patient-worn monitor). This patient data may be continuous monitoring data for one or more patients. A mobile application (optionally a browser application) on the clinician device can enable the clinician to view continuous monitoring data for multiple patients, as well as view and respond to alarms and alerts, all from the clinician device, regardless of location.

Abstract: A system and method of keyword spotting using two neural networks is disclosed. The system is in sleep mode most of the time, and wakes up periodically. Upon waking, a limited duration of audio is examined. This may be performed using an auxiliary neural network. If any audio activity is detected in this duration, the system fully wakes and examines a longer duration of audio for keywords. The keyword spotting is also performed by the main neural network, which may be a convolutional neural network (CNN).

Abstract: An integrated circuit including an input terminal and an output terminal, signal generator circuitry that generates a pseudo-random digital signal provided at the output terminal, and comparator circuitry that compares an input signal received via the input terminal with the pseudo-random digital signal for providing a tamper detection signal indicative thereof. The signal generator circuitry may be a pseudo-random binary sequence generator or may be a linear-feedback shift register with software triggered reloading. The comparator circuitry may include a Boolean logic exclusive-OR gate for comparing the output and input signals. A method of detecting tampering including generating and providing a pseudo-random digital signal at an output terminal and comparing an input signal received via an input terminal with the pseudo-random digital signal for providing a tamper detection signal indicative thereof.

Abstract: An apparatus includes an array processor to process array data. The array data are arranged in a memory. The array data are specified with programmable per-dimension size and stride values.

Abstract: A system and method of determining the angle of arrival or departure using a neural network is disclosed. The system collects a plurality of I and Q samples as a packet containing a constant tone extension is being received. The I and Q samples are used to form I and Q arrays, which are used as the input to the neural network. The neural network produces a first output representative of the azimuth angle and a second output representative of the elevation angle. In certain embodiments, the neural network is capable of detecting a plurality of angles, where, for each angle, there are three outputs, a first output representative of the azimuth angle, a second output representative of the elevation angle and a third output representative of the relative amplitude. In some embodiments, the neural network is configured to determine the carrier frequency offset of an incoming signal as well.

Abstract: A switch sensor for sensing a state of a switch including a programmable memory, pulse generation circuitry, and comparator circuitry. The memory stores a state value indicative of a detected state of the switch. The pulse generation circuitry provides a pulse-train voltage signal to a first end of the switch, in which the pulse-train voltage signal is toggled between an active state for switch state detection and an inactive state for conserving power. A second terminal of the switch is coupled through resistive circuitry to a supply voltage node and may be coupled to an input terminal of the sensor. The comparator circuitry compares a state of the input terminal with the state value when the pulse-train voltage signal is in the active state for providing a state change signal indicative thereof.

Abstract: A switch sensor for sensing a state of a switch including a programmable memory, pulse generation circuitry, and comparator circuitry. The memory stores a state value indicative of a detected state of the switch. The pulse generation circuitry provides a pulse-train voltage signal to a first end of the switch, in which the pulse-train voltage signal is toggled between an active state for switch state detection and an inactive state for conserving power. A second terminal of the switch is coupled through resistive circuitry to a supply voltage node and may be coupled to an input terminal of the sensor. The comparator circuitry compares a state of the input terminal with the state value when the pulse-train voltage signal is in the active state for providing a state change signal indicative thereof.

Abstract: An integrated circuit including an input terminal and an output terminal, signal generator circuitry that generates a pseudo-random digital signal provided at the output terminal, and comparator circuitry that compares an input signal received via the input terminal with the pseudo-random digital signal for providing a tamper detection signal indicative thereof. The signal generator circuitry may be a pseudo-random binary sequence generator or may be a linear-feedback shift register with software triggered reloading. The comparator circuitry may include a Boolean logic exclusive-OR gate for comparing the output and input signals. A method of detecting tampering including generating and providing a pseudo-random digital signal at an output terminal and comparing an input signal received via an input terminal with the pseudo-random digital signal for providing a tamper detection signal indicative thereof.

Abstract: A system and method of recording and transmitting compressed audio signals over a network is disclosed. The end node device first converts the audio signal to a spectrogram, which is commonly used by machine learning algorithms to perform speech recognition. The end node device then compresses the spectrogram prior to transmission. In certain embodiments, the compression is performed using Discrete Cosine Transforms (DCT). Furthermore, in some embodiments, the DCT is performed on the difference between two columns of the spectrogram. Further, in some embodiments, a function that replaces values below a predetermined threshold with zeroes in the Encoded Spectrogram is utilized. These functions may be performed in hardware or software.

Abstract: A system and method of recording and transmitting compressed audio signals over a network is disclosed. The end node device first converts the audio signal to a spectrogram, which is commonly used by machine learning algorithms to perform speech recognition. The end node device then compresses the spectrogram prior to transmission. In certain embodiments, the compression is performed using Discrete Cosine Transforms (DCT). Furthermore, in some embodiments, the DCT is performed on the difference between two columns of the spectrogram. Further, in some embodiments, a function that replaces values below a predetermined threshold with zeroes in the Encoded Spectrogram is utilized. These functions may be performed in hardware or software.

Abstract: A system and method of keyword spotting using two neural networks is disclosed. The system is in sleep mode most of the time, and wakes up periodically. Upon waking, a limited duration of audio is examined. This may be performed using an auxiliary neural network. If any audio activity is detected in this duration, the system fully wakes and examines a longer duration of audio for keywords. The keyword spotting is also performed by the main neural network, which may be a convolutional neural network (CNN).

Abstract: A system and method of determining the angle of arrival or departure using a neural network is disclosed. The system collects a plurality of I and Q samples as a packet containing a constant tone extension is being received. The I and Q samples are used to form I and Q arrays, which are used as the input to the neural network. The neural network produces a first output representative of the azimuth angle and a second output representative of the elevation angle. In certain embodiments, the neural network is capable of detecting a plurality of angles, where, for each angle, there are three outputs, a first output representative of the azimuth angle, a second output representative of the elevation angle and a third output representative of the relative amplitude. In some embodiments, the neural network is configured to determine the carrier frequency offset of an incoming signal as well.

Abstract: An approach is provided for data processing methods wherein a PHY layer transmit operation is constructed by aggregating MAC layer data units (MPDUs) by means of a linked list. A link list of TX descriptors can be formed separately from the payloads. In order to minimize processor speed rates, the next transmission buffer is pre-fetched whenever appropriate. Interlocks are used to prevent conflict on descriptor fetches and payload fetches.

Abstract: An approach is provided for generating response frames. Incoming frames are processed by a receive controller to determine type and attributes. Based on the type and the attributes of the incoming frame, a response frame is constructed and transmitted by a transmit controller. A response frame is constructed by setting values in a frame template. A block ACK can be implemented by means of a block ACK scoreboard.

Abstract: An integrated circuit includes a tamper sensor that has plurality of state circuits. Each of the plurality of state circuits has a respective output that provides a respective logic state. When operating properly, the respective logic state is toggled in response to a clock signal. The respective logic state fails to toggle in response to a respective fault injection. The tamper sensor has an output that provides a fault signal in response to a difference in the respective logic state of the plurality of state circuits. Additionally, the integrated circuit includes a protected circuit, as well as a tamper response circuit. The tamper response circuit is connected to the tamper sensor and to the protected circuit. The tamper response circuit executes a protection operation to secure the protected circuit in response to the fault signal.

Abstract: An integrated circuit includes a tamper sensor that has plurality of state circuits. Each of the plurality of state circuits has a respective output that provides a respective logic state. When operating properly, the respective logic state is toggled in response to a clock signal. The respective logic state fails to toggle in response to a respective fault injection. The tamper sensor has an output that provides a fault signal in response to a difference in the respective logic state of the plurality of state circuits. Additionally, the integrated circuit includes a protected circuit, as well as a tamper response circuit. The tamper response circuit is connected to the tamper sensor and to the protected circuit. The tamper response circuit executes a protection operation to secure the protected circuit in response to the fault signal.

Abstract: A processor, such as a low-cost microcontroller unit, uses a DMA controller to facilitate direct memory transactions between hardware subsystems independently of the CPU. To enable those transactions to be carried out security, gateways are provided to the DMA controller and peripheral bridge. The gateways, which have access to multiple access policies, switch between those policies depending on a hardware context and/or subcontext, such as the bus master originating the transaction and/or the DMA channel associated with the transaction. The gateways are operable to administer those policies independently of the CPU. In various implementations, gateways are provided for the DMA controller, the peripheral bridge, and/or individual peripherals. The processor is able to support secure, fully containerized operations involving its peripherals without constant CPU intervention.

Abstract: A processor, such as a low-cost microcontroller unit, uses a DMA controller to facilitate direct memory transactions between hardware subsystems independently of the CPU. To enable those transactions to be carried out security, gateways are provided to the DMA controller and peripheral bridge. The gateways, which have access to multiple access policies, switch between those policies depending on a hardware context and/or subcontext, such as the bus master originating the transaction and/or the DMA channel associated with the transaction. The gateways are operable to administer those policies independently of the CPU. In various implementations, gateways are provided for the DMA controller, the peripheral bridge, and/or individual peripherals. The processor is able to support secure, fully containerized operations involving its peripherals without constant CPU intervention.

Abstract: Techniques for performing automatic antenna sector-level sweep switching are described herein. According to an embodiment, an apparatus comprises a lookup table for storing a set of antenna configuration entries and a sector-level sweep (SLS) controller implemented in hardware that is communicatively coupled to the lookup table. The SLS sweep controller is operative to read an antenna configuration entry from the set of antenna configuration entries stored in the lookup table and output control signals to configure a set of one or more antennas based on the antenna configuration entry. The SLS controller is further operative to switch between different antenna configuration entries in the set of antenna configuration entries stored in the lookup table in response to a signal from a timing source thereby periodically changing the configuration of the set of one or more antennas.

Abstract: An approach is provided for data processing methods wherein a PHY layer transmit operation is constructed by aggregating MAC layer data units (MPDUs) by means of a linked list. A link list of TX descriptors can be formed separately from the payloads. In order to minimize processor speed rates, the next transmission buffer is pre-fetched whenever appropriate. Interlocks are used to prevent conflict on descriptor fetches and payload fetches.