Abstract: As part of a compute instance migration, a compute instance which was executing at a first server begins execution at a second server before at least some state information of the compute instance has reached the second server. In response to a determination that a particular page of state information is not present at the second server, a migration manager running at one or more offload cards of the second server causes the particular page to be transferred to the second server via a network channel set up between the offload cards of both servers, and stores the page into main memory of the second server.

Abstract: A method includes, in a virtualized processing system, generating a local value of a first counter. The local value is accessible while executing in a first mode of the virtualized processing system. The local value is generated based on a value of a second counter and a ratio of a rate of the first counter to a rate of the second counter. The first counter is inaccessible while executing in the first mode of the virtualized processing system and accessible while executing in a second mode of the virtualized processing system. The first mode may be a guest mode and the second mode may be a host mode. The first counter may be an ACPI Power Management Timer. The second counter may be a Time Stamp Counter.

Abstract: A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated hardware-emulation environment for execution of one or more corresponding guest operating systems (OSs). Each guest OS, as well as the hypervisor itself, has an associated address space, identified with a corresponding “WorldID.” Further, each virtual machine and the hypervisor can manage multiple lower-level address spaces, identified with a corresponding “address space identifier” or “ASID”. The address translation logic of the processing system translates the WorldID and ASID of the current address space context of the processing system to corresponding WorldID and ASID search keys, which have fewer bits than the original identifiers and thus require less complex translation lookaside buffer (TLB) hit logic.

Abstract: A processor including a virtual memory paging mechanism. The virtual memory paging mechanism enables an operating system operating on the processor to use pages of a first size and a second size, the second size being greater than the first size. The mechanism further enables the operating system to use superpages including two or more contiguous pages of the first size. The size of a superpage is less than the second size. The processor further includes a page table having a separate entry for each of the pages included in each superpage. The operating system accesses each superpage using a single virtual address. The mechanism interprets a single entry in a translation lookaside buffer TLB as referring to a region of memory comprising a set of pages that correspond to a superpage in response to detecting a superpage enable indicator associated with the entry in the TLB is asserted.

Abstract: A method includes, in a virtualized processing system, generating a local value of a first counter. The local value is accessible while executing in a first mode of the virtualized processing system. The local value is generated based on a value of a second counter and a ratio of a rate of the first counter to a rate of the second counter. The first counter is inaccessible while executing in the first mode of the virtualized processing system and accessible while executing in a second mode of the virtualized processing system. The first mode may be a guest mode and the second mode may be a host mode. The first counter may be an ACPI Power Management Timer. The second counter may be a Time Stamp Counter.

Abstract: A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated hardware-emulation environment for execution of one or more corresponding guest operating systems (OSs). Each guest OS, as well as the hypervisor itself, has an associated address space, identified with a corresponding “WorldID.” Further, each virtual machine and the hypervisor can manage multiple lower-level address spaces, identified with a corresponding “address space identifier” or “ASID”. The address translation logic of the processing system translates the WorldID and ASID of the current address space context of the processing system to corresponding WorldID and ASID search keys, which have fewer bits than the original identifiers and thus require less complex translation lookaside buffer (TLB) hit logic.

Abstract: A processor including a virtual memory paging mechanism. The virtual memory paging mechanism enables an operating system operating on the processor to use pages of a first size and a second size, the second size being greater than the first size. The mechanism further enables the operating system to use superpages including two or more contiguous pages of the first size. The size of a superpage is less than the second size. The processor further includes a page table having a separate entry for each of the pages included in each superpage. The operating system accesses each superpage using a single virtual address. The mechanism interprets a single entry in a translation lookaside buffer TLB as referring to a region of memory comprising a set of pages that correspond to a superpage in response to detecting a superpage enable indicator associated with the entry in the TLB is asserted.