Abstract: The invention relates to a method and timing recovery circuit for recovering a sampling clock from a serial data stream encoded using Pulse-Amplitude-Modulation, comprising: applying a filter pattern decoder to detected symbol sequence at more than two adjacent data symbols, particularly to the detected symbol patterns of four adjacent samples {circle around (y)}(k?2), {circle around (y)}(k?1), {circle around (y)}(k), {circle around (y)}(k+1), and calculating an estimated phase error e(k).

Abstract: A multi-mode line driver circuit supporting different communication standards includes an output for the network connection, and driver elements connected in parallel to the output. Each driver element is connected to a positive and negative supply voltage, and includes a resistor, a first switch and a second switch. The resistor is connected to the output and via the first switch to the positive supply voltage and via the second switch to the negative supply voltage. The driver circuit also includes at least one coding block with an input for a digital signal to be transmitted over the network connection. The coding block provides control signals for the first switch and the second switch for connecting the resistor of each driver element to the positive supply voltage or the negative supply voltage. The digital signal of the multi-mode line driver circuit is coded according to a communication standard.

Abstract: A method for an improved characterization of standard cells in a circuit design process is disclosed. Adaptive body biasing is considered during the design process by using simulation results of a cell set, a data-set for performance of the cell set, and a data-set for a hardware performance for a slow, typical and fast circuit property. Static deviations in a supply voltage are considered by determining a reference performance of a cell and a reference hardware performance monitor value at a PVT corner. A virtual regulation and adapting of body bias voltages of the cell set is performed such that the reference performance of the cell or the reference hardware performance monitor value will be reached at each PVT corner and for compensating the static deviation in the supply voltage. The results are provided in a library file.

Abstract: A method and an apparatus for reducing an effect of local process variations of a digital circuit on a hardware performance monitor includes measuring a set of performance values (c1, c2 . . . cn) of the digital circuit by n identical hardware performance monitors, where n is a natural number greater than 1, determining an average value cmean of the measured performance values (c1, c2 . . . cn), as an approximation of an ideal performance value c0, selecting one performance value cj of the set of performance values (c1, c2 . . . cn) by a controller, comparing the performance value cj with a reference value cref by a controller the controller, resulting in a deviation value ?c, and controlling an actuator by using the deviation ?c for regulating the local global process variations to the approximation cmean of the ideal performance value c0.

Abstract: The invention relates to a multicore processor and a method for dynamically adjusting a supply voltage and a clock frequency, with which an individual supply voltage and dock frequency adjustment, which depends on a current computing load, is facilitated for each processor core of a multicore processor. Thus, an assembly is disclosed where a local queue memory unit which is connected to the processor core, the internal memory unit, and the level converter is arranged in a voltage-variable region of the processor element in order to store events to be processed by the processor core. The invention is also directed to a method in that the required supply voltage U and the required clock frequency f are adjusted for each cycle in a controlled manner by the processor core of the respective processor element depending on the detection of a number of events to be processed which are stored in an internal queue memory unit.

Abstract: A RF frontend interface for a 61 GHz radio powered communication tag device with a built-in antenna includes an IC embedded in a silicon die with a top metallization layer and a dielectric resonant body linked to the silicon die. A high impedance antenna with two feed points is embedded into the top metallization layer and a RF rectifier and multiplier circuit connected to the antenna feed is integrated in the silicon die and symmetrically placed between the antenna feed points configured to stabilize the antenna resonant frequency with its inherent capacity against varying surrounding materials and generate a positive and negative DC output supply voltage against a bulk potential of the silicon die for directly operating a digital circuit in FDSOI technology embedded in the silicon die. The resonant body is configured to work as a wavelength translator in between the antenna and free space.

Abstract: The invention relates to a multicore processor and a method for dynamically adjusting a supply voltage and a clock frequency, with which an individual supply voltage and dock frequency adjustment, which depends on a current computing load, is facilitated for each processor core of a multicore processor. Thus, an assembly is disclosed where a local queue memory unit which is connected to the processor core, the internal memory unit, and the level converter is arranged in a voltage-variable region of the processor element in order to store events to be processed by the processor core. The invention is also directed to a method in that the required supply voltage U and the required clock frequency f are adjusted for each cycle in a controlled manner by the processor core of the respective processor element depending on the detection of a number of events to be processed which are stored in an internal queue memory unit.

Abstract: A method and a circuit for adaptive regulation of body bias voltages controlling nmos and pmos transistors of an integrated circuit includes a digital circuit, a counter, a control unit and a charge pump. A first ring oscillator monitor measures a period duration of nmos transistors and a second ring oscillator monitor measures a period duration of pmos transistors. A first closed control loop adaptively regulates the performance cn of the body bias controlled nmos transistors of the digital circuit by comparing the measured period duration of nmos dominated first ring oscillator monitor to a period duration of a reference clock and a second closed control loop adaptively regulating the performance cp of the body bias controlled pmos transistors of the digital circuit by comparing the measured period duration of pmos dominated second ring oscillator monitor to the period duration of the reference clock.

Abstract: A method and a circuit for adaptive regulation of body bias voltages controlling nmos and pmos transistors of an integrated circuit includes a digital circuit, a counter, a control unit and a charge pump. A first ring oscillator monitor measures a period duration of nmos transistors and a second ring oscillator monitor measures a period duration of pmos transistors. A first closed control loop adaptively regulates the performance cn of the body bias controlled nmos transistors of the digital circuit by comparing the measured period duration of nmos dominated first ring oscillator monitor to a period duration of a reference clock and a second closed control loop adaptively regulating the performance cp of the body bias controlled pmos transistors of the digital circuit by comparing the measured period duration of pmos dominated second ring oscillator monitor to the period duration of the reference clock.

Abstract: A method and an apparatus for reducing the effect of local process variations of a digital circuit on a hardware performance monitor includes measuring a set of performance values cn of the digital circuit by n identical hardware performance monitors, where n is a natural number greater than 1, determining an average value cmean of the measured performance values cn, as an approximation of an ideal performance value c0, selecting one performance value cj of the set of performance values cn by a signal converter, comparing the performance value cj with a reference value cref by a controller, resulting in a deviation value ?c, and controlling an actuator by using the deviation ?c for regulating the local global process variations to the approximation cmean of the ideal performance value c0.

Abstract: An apparatus and a method for generation and adaptive regulation of body bias voltages of an integrated circuit efficiently generates control voltages for active body biasing The apparatus includes a digital circuit, a counter, a control unit and at least one charge pump. The control unit and the digital circuit are connected in a closed control loop, and the digital circuit comprises at least one hardware performance monitor to monitor a timing of a body bias voltage. The control loop is formed by a control path comprising the at least one charge pump, the hardware performance monitor and the control unit. The charge pump is controllably connected to the control unit to adjust the charge pump for generation and adaptive regulation of the body bias voltage according to a timing frequency difference between an output signal of the hardware performance monitor and a reference clock signal.

Abstract: A RF frontend interface for a 61 GHz radio powered communication tag device with a built-in antenna includes an IC embedded in a silicon die with a top metallization layer and a dielectric resonant body linked to the silicon die. A high impedance antenna with two feed points is embedded into the top metallization layer and a RF rectifier and multiplier circuit connected to the antenna feed is integrated in the silicon die and symmetrically placed between the antenna feed points configured to stabilize the antenna resonant frequency with its inherent capacity against varying surrounding materials and generate a positive and negative DC output supply voltage against a bulk potential of the silicon die for directly operating a digital circuit in FDSOI technology embedded in the silicon die. The resonant body is configured to work as a wavelength translator in between the antenna and free space.

Abstract: A method for an improved characterization of standard cells in a circuit design process is disclosed. Adaptive body biasing is considered during the design process by using simulation results of a cell set, a data-set for performance of the cell set, and a data-set for a hardware performance for a slow, typical and fast circuit property. Static deviations in a supply voltage are considered by determining a reference performance of a cell and a reference hardware performance monitor value at a PVT corner. A virtual regulation and adapting of body bias voltages of the cell set is performed such that the reference performance of the cell or the reference hardware performance monitor value will be reached at each PVT corner and for compensating the static deviation in the supply voltage. The results are provided in a library file.

Abstract: An apparatus and a method for generation and adaptive regulation of body bias voltages of an integrated circuit efficiently generates control voltages for active body biasing The apparatus includes a digital circuit, a counter, a control unit and at least one charge pump. The control unit and the digital circuit are connected in a closed control loop, and the digital circuit comprises at least one hardware performance monitor to monitor a timing of a body bias voltage. The control loop is formed by a control path comprising the at least one charge pump, the hardware performance monitor and the control unit. The charge pump is controllably connected to the control unit to adjust the charge pump for generation and adaptive regulation of the body bias voltage according to a timing frequency difference between an output signal of the hardware performance monitor and a reference clock signal.

Abstract: A method for generating random numbers on multiprocessor systems and a multiprocessor system for generating true random numbers, using the method, generate truly random numbers with high entropy in a multiprocessor system with little additional effort to chip area and power dissipation. The method includes the steps of: measuring a phase error signal of a clock generator circuit of a first and a second processing unit respectively, forwarding the phase error signal of the respective clock generator circuit of the first and second processing unit to a true random network, combining the phase error signal of the clock generator circuit of the first processing unit and the phase error signal of the clock generator circuit of the second processing unit in the true random network to random bit streams, picking-up a random bit stream of the true random network, passing the respective random bit stream back to a random generator of the respective processing unit for outputting true random.

Abstract: A method for generating random numbers on multiprocessor systems and a multiprocessor system for generating true random numbers, using the method, generate truly random numbers with high entropy in a multiprocessor system with little additional effort to chip area and power dissipation. The method includes the steps of: measuring a phase error signal of a clock generator circuit of a first and a second processing unit respectively, forwarding the phase error signal of the respective clock generator circuit of the first and second processing unit to a true random network, combining the phase error signal of the clock generator circuit of the first processing unit and the phase error signal of the clock generator circuit of the second processing unit in the true random network to random bit streams, picking-up a random bit stream of the true random network, passing the respective random bit stream back to a random generator of the respective processing unit for outputting true random.

Abstract: A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.

Abstract: A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.