Abstract: This invention disclosure is an electrical outlet receptacle containing the high voltage AC side and low voltage DC power supply used typically for charging and/or powering portable electronic devices. The charge connector for interfacing with the portable device is contained in a removable module. Furthermore the removable module may contain a retractable charge cord or charge cords, charge status indicator lights, power supply switches, and it also may contain a portion of the power supply control circuitry to provide the particular power and signaling required to interface with the specific portable device. The other portion of the power supply and control circuitry would be contained in the fixed portion of the receptacle and/or the electrical box. Finally there may be additional heat sinks to provide enough thermal dissipation from the power supply.

Abstract: This invention disclosure is an electrical outlet receptacle containing the high voltage AC side and low voltage DC power supply used typically for charging and/or powering portable electronic devices. The charge connector for interfacing with the portable device is contained in a removable module. Furthermore the removable module may contain a retractable charge cord or charge cords, charge status indicator lights, power supply switches, and it also may contain a portion of the power supply control circuitry to provide the particular power and signaling required to interface with the specific portable device. The other portion of the power supply and control circuitry would be contained in the fixed portion of the receptacle and/or the electrical box. Finally there may be additional heat sinks to provide enough thermal dissipation from the power supply.

Abstract: A high speed multi-lane serial interface and method for constructing frames for such an interface are provided. Frames are constructed for transmission on a multi-lane serial interface. For each of a plurality of transmit channels, packets are fragmented into fragments. Meta-frames are generated having a size defined by a constant meta-frame length×number of lanes, each frame having a meta-frame separator and a payload. Per-transmit channel flow control information is received. Each payload has a plurality of bursts, each burst comprising a burst control word and an associated data burst, the burst control word identifying one of said transmit channels to be transmitted on the associated data burst, each data burst comprising one of the fragments for the transmit channel identified in the associated burst control word. The channels to transmit in a given meta-frame are selected as a function of the received flow control information.

Abstract: Port multiplexing apparatus and methods are disclosed. Time slots in a time division multiplexing (TDM) scheme are allocated to transfer signals such as Ethernet or Fiber Channel packets associated with ports of a signal processing device. Signals associated with multiple ports are transferred between those ports and another signal processing device over a single logical link in accordance with the time slot allocation. An indication of the time slot allocation may also be transferred on the link, illustratively by replacing protocol overhead traffic to be transmitted on the link with allocation information. At a receiver, the replaced protocol overhead traffic may be substituted back into a received multiplexed signal. A port multiplexing apparatus may be controllable to operate in a multiplexing mode or in a non-multiplexing mode. Aspects of the invention may also be embodied in other forms, such as in a data structure stored on a machine-readable medium.

Abstract: A high speed multi-lane serial interface and method for constructing frames for such an interface are provided. Frames are constructed for transmission on a multi-lane serial interface. For each of a plurality of transmit channels, packets are fragmented into fragments. Meta-frames are generated having a size defined by a constant meta-frame length×number of lanes, each frame having a meta-frame separator and a payload. Per-transmit channel flow control information is received. Each payload has a plurality of bursts, each burst comprising a burst control word and an associated data burst, the burst control word identifying one of said transmit channels to be transmitted on the associated data burst, each data burst comprising one of the fragments for the transmit channel identified in the associated burst control word. The channels to transmit in a given meta-frame are selected as a function of the received flow control information.

Abstract: A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible for executing a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. The 32-bit instruction set architecture includes “prepare to branch” instructions that allow target addresses for branch instructions to be set up in advance of the branch. The 32-bit prepare to branch and branch instructions are combined to execute a 16-bit branch instruction coupled with a 16-bit Delay Slot instruction.