Abstract: An improved branch instruction and associated branch control instruction are provided for optimizing handling of branch operations within a pipelined processor. The branch control instruction is adapted so that it can precede the branch instruction in a program sequence and provides branch target address computation information so that branch target addresses can be computed in advance of execution of one or more associated branch instructions. The branch control instruction also includes its own branch instruction prediction bit for specifying to a prefetcher within the processor whether a common branch instruction is likely to be needed by the processor, as well as a ranking field for specifying a preloading priority for the particular common branch instruction.

Abstract: A dual mode branch and branch control system and method is disclosed for accommodating a processor that can operate in either of two operating modes, each using a different type of branch instruction. In a first instruction set, a first type branch instruction includes a separate branch instruction and a branch control instruction, while in the second instruction set, a second type branch instruction includes only a branch instruction. The processor is optimized to handle the first instruction set so that the branch instruction is arrangeable in a program sequence so that an execution unit in the processor can compute a branch target address based on the branch control instruction without a latency penalty. The first type branch instructions also include a folded-compare format, while the second type branch instructions have separated compare and branch instructions.

Abstract: A two level branch prediction system and method is disclosed for controlling instruction flow in a pipelined processor. A first prediction indicator associated with a branch instruction specifies whether a particular branch condition is likely to be satisfied. A second prediction indicator associated with a branch control instruction specifies whether a particular branch target instruction is likely to be needed by one or more of the branch instructions. The first prediction indicator is used to load branch target instructions as they are needed in response to decoding a branch instruction, while the second prediction indicator is used by prefetching logic within the processor to determine whether a particular branch target instruction should be speculatively loaded even before the associated branch instruction is executed.