Abstract: A circuit unit in a chip includes a main circuit portion and a configurable portion. The configurable portion includes an output stage, a plurality of configurable stages, and a configurable metal layer. The configurable stages are configured to be connected in sequence to the output stage. The configurable metal layer is connected to the output stage. The main circuit portion is configured to be adjacent to and connected to the output stage of the configurable portion. A driving strength of the circuit unit is determined based on a connection relationship between each of the plurality of configurable stages and the configurable metal layer.

Abstract: A processor and accompanying program are disclosed which utilize branch control instructions in cooperation with branch instructions to reduce branch latency. The branch control instruction and branch instruction have a format/structure that is designed to execute flexibly and efficiently by making use of separate dedicated target address and target branch instruction register sets used by a pipeline within the processor.