Abstract: An improved branch instruction and associated branch control instruction are provided for optimizing handling of branch operations within a pipelined processor. The branch control instruction is adapted so that it can precede the branch instruction in a program sequence and provides branch target address computation information so that branch target addresses can be computed in advance of execution of one or mote associated branch instructions. Because branch target address computation information is disassociated from the actual branch instruction, more space is available within the branch instruction itself to permit additional new types of operations, such as folded-compare, register to register comparisons (including a compare to a zero valued register), predicate evaluations, etc.

Abstract: A system and method for implementing a computing system and associated programs with optimized branch instruction execution is disclosed. Branch operations are divided into two parts, with a branch control (prepare to branch) preceeding a branch instruction in the instruction stream, so that a pipeline in the computing system can be set up in advance to load appropriate target instructions. In this manner, instruction flow can be easily re-directed if the branch instruction is accurately predicted. Predictions on the branch condition are used to speculatively prefetch and load instructions as needed. In most cases, branch execution penalties caused by target address calculation latencies, instruction cache latencies and/or mis-predictions, can be significantly reduced.