Abstract: A circuit for generating a swept source optical coherence tomography (SS-OCT) imaging calibration clock. The circuit comprises a first photodetector configured to convert an SS-OCT optical calibration signal to an SS-OCT electrical calibration signal, a first analog-to-digital converter (ADC) coupled to the first photodetector and configured to convert the SS-OCT electrical calibration signal to a sequence of SS-OCT calibration signal digital values, a processing unit coupled to the first ADC that, when initiated, is configured to demodulate the sequence of SS-OCT calibration signal digital values to obtain a sequence of SS-OCT wave number digital values, where each SS-OCT wave number digital value corresponds to one of the SS-OCT calibration signal digital values, and a level crossing sampler that is configured to track a wave number associated with the SS-OCT optical calibration signal and to generate an SS-OCT calibration clock pulse.

Abstract: A circuit for generating a swept source optical coherence tomography (SS-OCT) imaging calibration clock. The circuit comprises a first photodetector configured to convert an SS-OCT optical calibration signal to an SS-OCT electrical calibration signal, a first analog-to-digital converter (ADC) coupled to the first photodetector and configured to convert the SS-OCT electrical calibration signal to a sequence of SS-OCT calibration signal digital values, a processing unit coupled to the first ADC that, when initiated, is configured to demodulate the sequence of SS-OCT calibration signal digital values to obtain a sequence of SS-OCT wave number digital values, where each SS-OCT wave number digital value corresponds to one of the SS-OCT calibration signal digital values, and a level crossing sampler that is configured to track a wave number associated with the SS-OCT optical calibration signal and to generate an SS-OCT calibration clock pulse.

Abstract: A continuous-time delta-sigma analog-to-digital converter (ADC) is disclosed. The ADC includes a loop filter, a loop quantizer, and a clock-jitter tolerant digital-to-analog converter (DAC). The clock-jitter tolerant DAC includes a dual switched-current (SI) DAC, a switched-capacitor (SC) DAC, an adder, and a switched-capacitor-resistor (SCR) injection circuit. The dual SI DAC provides two identical analog signals from the feedback digital signal of a loop quantizer within the ADC. The SC DAC provides an error-free reference signal from the feedback digital signal. The adder subtracts one of the two analog signals from the error-free reference signal to obtain an inverted jitter-induced error signal. The SCR injection circuit then injects the inverted jitter-induced error signal, delayed by one clock-cycle, in the form of a half-delay return-to-zero exponentially decaying waveform into the loop filter.

Abstract: A continuous-time delta-sigma analog-to-digital converter (ADC) is disclosed. The ADC includes a loop filter, a loop quantizer, and a clock-jitter tolerant digital-to-analog converter (DAC). The clock-jitter tolerant DAC includes a dual switched-current (SI) DAC, a switched-capacitor (SC) DAC, an adder, and a switched-capacitor-resistor (SCR) injection circuit. The dual SI DAC provides two identical analog signals from the feedback digital signal of a loop quantizer within the ADC. The SC DAC provides an error-free reference signal from the feedback digital signal. The adder subtracts one of the two analog signals from the error-free reference signal to obtain an inverted jitter-induced error signal. The SCR injection circuit then injects the inverted jitter-induced error signal, delayed by one clock-cycle, in the form of a half-delay return-to-zero exponentially decaying waveform into the loop filter.

Abstract: A system is provided. The system comprises a transform domain radio receiver comprising a plurality of reconfigurable processing paths coupled to a radio frequency signal input, each reconfigurable processing path implementing a down converter, a low-pass filter, and an integrator and wherein a frequency selectivity of the processing path is reconfigurable. The system also comprises a control unit to configure a frequency selectivity of the plurality of parallel reconfigurable processing paths.

Abstract: Included are embodiments of a method for converting a received analog signal into a digital signal. Some embodiments of the method can include receiving an analog signal; periodically dividing the received analog signal into a plurality of discrete signals at a predetermined interval, wherein each of the plurality of divided signals is associated with a voltage; and quantizing the voltage associated with at least one of the plurality of divided signals. Other systems and methods are also provided.