Abstract: A voltage monitor circuit comprises: a monitored voltage input (42); a reference capacitor (32) arranged to be able to store a value of the monitored voltage as a reference capacitor voltage; a timeout capacitor (34) arranged to be able to store a value of the monitored voltage as a timeout capacitor voltage. The timeout capacitor undergoes a higher leakage than the reference capacitor. The voltage monitor circuit also comprises a comparator (2) arranged to: compare the monitored voltage to the reference capacitor voltage; compare the timeout capacitor voltage to the reference capacitor voltage; and produce a logic signal on an output (9) of the comparator based on said comparisons, the logic signal having a first logic value at least if the reference capacitor voltage is lower than or equal to both the monitored voltage and the timeout capacitor voltage.

Abstract: A voltage monitor circuit comprises: a monitored voltage input (42); a reference capacitor (32) arranged to be able to store a value of the monitored voltage as a reference capacitor voltage; a timeout capacitor (34) arranged to be able to store a value of the monitored voltage as a timeout capacitor voltage. The timeout capacitor undergoes a higher leakage than the reference capacitor. The voltage monitor circuit also comprises a comparator (2) arranged to: compare the monitored voltage to the reference capacitor voltage; compare the timeout capacitor voltage to the reference capacitor voltage; and produce a logic signal on an output (9) of the comparator based on said comparisons, the logic signal having a first logic value at least if the reference capacitor voltage is lower than or equal to both the monitored voltage and the timeout capacitor voltage.

Abstract: A start-up circuit arranged to initialize a circuit portion with a zero stable point and a non-zero stable point. The start-up circuit includes: a capacitive voltage divider including a first capacitor and a second capacitor that generate a divider bias voltage at a divider node; a differential amplifier including first and second amplifier inputs and an amplifier output connected to the divider node; a first driver transistor with its gate terminal connected to the divider node, and its drain terminal connected to a first start-up output and the first amplifier input; and a second driver transistor with its gate terminal connected to the divider node, and its drain terminal connected to a second start-up output and the second amplifier input. The differential amplifier controls the divider bias voltage and drives the circuit portion to the non-zero stable point.

Abstract: A start-up circuit (2) arranged to initialise a circuit portion (4) with a zero stable point (200) and a non-zero stable point (202). The start-up circuit comprises: a capacitive voltage divider including a first capacitor (16) and a second capacitor (18) that generate a divider bias voltage at a divider node (48); a differential amplifier including first and second amplifier inputs (20, 22) and an amplifier output connected to the divider node; a first driver transistor (12) with its gate terminal connected to the divider node, and its drain terminal connected to a first start-up output and the first amplifier input; and a second driver transistor (14) with its gate terminal connected to the divider node, and its drain terminal connected to a second start-up output and the second amplifier input. The differential amplifier controls the divider bias voltage and drives the circuit portion to the non-zero stable point.