Abstract: A method for detecting a fault state of at least one battery cell of a battery having multiple battery cells. A cell voltage of a respective battery cell of the multiple battery cells is registered at a measurement time and a comparison value is determined as a function of at least one of the cell voltages and is compared to a provided first reference value. The fault state is detected as a function of a result of the comparison. A scatter value is determined, which represents a scatter of at least part of the cell voltages registered at the specific measurement time, and the fault state is determined as a function of the scatter value.

Abstract: A semiconductor device includes: a semiconductor body having an active region and an edge termination region between the active region and a side surface of the semiconductor body; a first portion including silicon and nitrogen; a second portion including silicon and nitrogen, the second portion being in direct contact with the first portion; and a front side metallization in contact with the semiconductor body in the active region. The first portion separates the second portion from the semiconductor body. An average silicon content in the first portion is higher than in the second portion. The front side metallization is interposed between the first portion and the semiconductor body in the active region but not in the edge termination region, and/or the first portion and the second portion are both present in the edge termination region but not in the active region.

Abstract: A method for detecting a fault state of at least one battery cell of a battery having multiple battery cells. A cell voltage of a respective battery cell of the multiple battery cells is registered at a measurement time and a comparison value is determined as a function of at least one of the cell voltages and is compared to a provided first reference value. The fault state is detected as a function of a result of the comparison. A scatter value is determined, which represents a scatter of at least part of the cell voltages registered at the specific measurement time, and the fault state is determined as a function of the scatter value.

Abstract: A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 ?m. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.

Abstract: A semiconductor device includes: a semiconductor body having an active region and an edge termination region between the active region and a side surface of the semiconductor body; a first portion including silicon and nitrogen; a second portion including silicon and nitrogen, the second portion being in direct contact with the first portion; and a front side metallization in contact with the semiconductor body in the active region. The first portion separates the second portion from the semiconductor body. An average silicon content in the first portion is higher than in the second portion. The front side metallization is interposed between the first portion and the semiconductor body in the active region but not in the edge termination region, and/or the first portion and the second portion are both present in the edge termination region but not in the active region.

Abstract: A semiconductor device includes a semiconductor body and a first portion including silicon and nitrogen. The first portion is in direct contact with the semiconductor body. A second portion including silicon and nitrogen is in direct contact with the first portion. The first portion is between the semiconductor body and the second portion. An average silicon content in the first portion is higher than in the second portion.

Abstract: Systems, methods, and computer-readable media are disclosed for dynamically determining relative product performance using quantitative values.

Abstract: A method for producing a wood veneer, where the wood veneer is provided as a decorative layer for a trim piece for a vehicle interior, wherein the molded part has at least one line element on a visible side, can involve the steps of a) providing a wood blank, b) generating two-dimensional cutting data by developing a designated three-dimensional shape of the wood veneer c) forming wood slats by cutting out the two-dimensional developed form of the wood veneer from the wood blank and slicing the two-dimensional developed form along the developed line elements on the basis of the two-dimensional cutting data, d) layering and gluing the cut wood slats to form a veneer block, e) compressing the wood slats and curing the veneer block, f) separating the veneer block into wood veneers. Moreover, the invention relates to a veneer block, a molded part, and corresponding methods of production.

Abstract: A power semiconductor device includes a semiconductor body having a front side surface, and a first passivation layer arranged above the front side surface. The first passivation layer is a polycrystalline diamond layer.

Abstract: A polyol component b) comprising: 20 to 40 wt % of polyetherester polyols B) having a functionality of 3.8 to 4.8, an OH number of 380 to 440 mg KOH/g and a fatty acid and/or fatty acid ester content of 8 to 17 wt %, based on the weight of polyetherester polyols B); 20 to 40 wt % of polyether polyols C) having a functionality of 3.7 to 4 and an OH number of 300 to 420 mg KOH/g; 20 to 40 wt % of one or more polyether polyols D) having a functionality of 4.5 to 6.5 and an OH number of 400 to 520 mg KOH/g; 0.5 to 5.5 wt % of catalysts E), 0.1 to 5 wt % of further auxiliaries and/or added-substance materials F), 0.5 to 5 wt % of water G); and also rigid polyurethane foams obtained therewith and use thereof for insulation and refrigeration applications.

Abstract: A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 ?m. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.

Abstract: A method for the hemostasis of perforating and bleeding vessel related to intracerebral hemorrhage (ICH) includes navigating an occlusion device into a parent artery and then deploying the occlusive device to transiently occlude bleeding vessels to reduce blood flow and local blood pressure until hemostasis is achieved, while maintaining flow within the parent artery. Embodiments of the occlusion device include a catheter, an expandable member sized for insertion into the mid-cerebral artery (MCA) and having a length sufficient to occlude at least one ostia of the lenticulostriate arteries (LSA), with a flow path for blood provided from a proximal side of the expandable member to a distal side of the expandable member, and a semi-permeable contacting member about the expandable member and adapted to be in contact with a wall of the MCA adjacent the ostia, the semi-permeable member permitting a reduce flow of blood through the ostia.

Abstract: A semiconductor device includes a semiconductor body and a first portion including silicon and nitrogen. The first portion is in direct contact with the semiconductor body. A second portion including silicon and nitrogen is in direct contact with the first portion. The first portion is between the semiconductor body and the second portion. An average silicon content in the first portion is higher than in the second portion.

Abstract: A method for manufacturing a high-voltage semiconductor device includes exposing a semiconductor substrate to a plasma to form a protective substance layer on the semiconductor substrate. A semiconductor device includes a semiconductor substrate and a protective substance layer on the semiconductor substrate.

Abstract: A method for producing a wood veneer, where the wood veneer is provided as a decorative layer for a trim piece for a vehicle interior, wherein the molded part has at least one line element on a visible side, can involve the steps of a) providing a wood blank, b) generating two-dimensional cutting data by developing a designated three-dimensional shape of the wood veneer c) forming wood slats by cutting out the two-dimensional developed form of the wood veneer from the wood blank and slicing the two-dimensional developed form along the developed line elements on the basis of the two-dimensional cutting data, d) layering and gluing the cut wood slats to form a veneer block, e) compressing the wood slats and curing the veneer block, f) separating the veneer block into wood veneers. Moreover, the invention relates to a veneer block, a molded part, and corresponding methods of production.

Abstract: A polyol component b) comprising: 20 to 40 wt % of polyetherester polyols B) having a functionality of 3.8 to 4.8, an OH number of 380 to 440 mg KOH/g and a fatty acid and/or fatty acid ester content of 8 to 17 wt %, based on the weight of polyetherester polyols B); 20 to 40 wt % of polyether polyols C) having a functionality of 3.7 to 4 and an OH number of 300 to 420 mg KOH/g; 20 to 40 wt % of one or more polyether polyols D) having a functionality of 4.5 to 6.5 and an OH number of 400 to 520 mg KOH/g; 0.5 to 5.5 wt % of catalysts E), 0.1 to 5 wt % of further auxiliaries and/or added-substance materials F), 0.5 to 5 wt % of water G); and also rigid polyurethane foams obtained therewith and use thereof for insulation and refrigeration applications.

Abstract: A method for the hemostasis of perforating and bleeding vessel related to intracerebral hemorrhage (ICH) includes navigating an occlusion device into a parent artery and then deploying the occlusive device to transiently occlude bleeding vessels to reduce blood flow and local blood pressure until hemostasis is achieved, while maintaining flow within the parent artery. Embodiments of the occlusion device include a catheter, an expandable member sized for insertion into the mid-cerebral artery (MCA) and having a length sufficient to occlude at least one ostia of the lenticulostriate arteries (LSA), with a flow path for blood provided from a proximal side of the expandable member to a distal side of the expandable member, and a semi-permeable contacting member about the expandable member and adapted to be in contact with a wall of the MCA adjacent the ostia, the semi-permeable member permitting a reduce flow of blood through the ostia.

Abstract: The present invention relates to polyols and the preparation and use thereof.

Abstract: The present invention relates to polyols and the preparation and use thereof.

Abstract: A dielectric layer is deposited on a working surface of a substrate, wherein the dielectric layer contains or consists of a dielectric polymer. The dielectric layer is partially cured. A portion of the partially cured dielectric layer is removed using a chemical mechanical polishing process. Then the curing of remnant portions of the partially cured dielectric layer is continued to form a dielectric structure. The partially cured dielectric layer shows high removal rates during chemical mechanical polishing. With remnant portions of the dielectric layer provided in cavities, high volume insulating structures can be provided in an efficient manner.