Abstract: A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other said local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

Abstract: A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

Abstract: Disclosed is an integrated circuit comprising a plurality of cores attached to at least one transmitter and receiver, an optical transmission network embedded within the wire levels of the integrated circuit, and wherein the transmitter and receivers send and receive data on the network. Also disclosed is a method of transmitting signals within an integrated circuit comprising an integrated circuit comprising a plurality of cores and optical paths, selecting an optical path from the plurality of optical paths for transmitting data, and transmitting the data on the selected optical path. Also disclosed is an integrated circuit comprising an optical transmission network, a plurality of cores, and a plurality of controllers, all three being operatively attached to each other.

Abstract: The disclosure presents a method of designing an integrated circuit having latches. The invention first prepares a logical design of logic devices and latches and then creates a physical design by positioning the logic devices and the latches within the integrated circuit based on the logical design. During the process of creating the physical design the invention eliminates redundant latches by combining latches which do not transition during the same clock cycle, latches which do not relate to the same logical function, latches which are in the same clock domain, and latches that are within a given physical proximity of each other. The invention determines whether latches transition during the same clock cycle by running a simulation of an initial physical design and recording the latches that transition during each clock cycle. The invention also determines whether an adequate timing slack exists between transitions of latches that do not transition during the same clock cycle.

Abstract: The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment of a segmented data line and then propagating the first data portion along a second segment of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line.

Abstract: A method and structure for an integrated circuit is disclosed. The invention includes a plurality of logic cores, a plurality of local hubs connected to said logic cores, and a plurality of global hubs connected to said local hubs. The local hubs and the global hubs transfer data between the logic cores.

Abstract: A processing system executing multiple programs and operating under control of an operating system, comprising a processor unit which includes a dispatch/decode unit under control of the operating system for dispatching and decoding instructions of the multiple programs, the instructions each including a program ID. The processor unit further comprises a plurality of execution units, each separately selectable by the operating system for receiving any of the instructions of the multiple programs from the dispatch/decode unit, wherein one of the execution units is executing an instruction from one of the multiple programs while another of the execution units is executing an instruction from another one of the multiple programs. The processor unit also comprises a retirement unit storing results of executed ones of the instructions uniquely in response to each program ID.

Abstract: A processing system executing multiple programs and operating under control of an operating system, comprising a processor unit which includes a dispatch/decode unit under control of the operating system for dispatching and decoding instructions of the multiple programs, the instructions each including a program ID. The processor unit further comprises a plurality of execution units, each separately selectable by the operating system for receiving any of the instructions of the multiple programs from the dispatch/decode unit, wherein one of the execution units is executing an instruction from one of the multiple programs while another of the execution units is executing an instruction from another one of the multiple programs. The processor unit also comprises a retirement unit storing results of executed ones of the instructions uniquely in response to each program ID.

Abstract: A logic circuit device and circuit design methodology includes a “split-book” logic circuit design having different active device sizes with outputs for connections to both critical and non-critical digital circuit paths. By using “split” book designs with separate input and output stages, better silicon utilization, power optimization, and performance results. This is because each split book is designed with multiple output buffers that may be configured to optimally drive critical and non-critical paths. During the power/performance optimization phase of the design, timing critical paths of the design are first identified, with each path being optimized on its own basis. First the input stage of the strand may be improved with a stronger drive on the input port of the book. Only the input port that has been linked to a critical path is updated. The other input pins are left at their default setting.

Abstract: A hybrid pipelined processor and associated processing methods are described for separately handling substantially concurrently in a time division manner multiple program instruction threads. The hybrid architecture includes an instruction fetch unit, an instruction decode unit and an execution unit. The execution unit includes multiple sets of register files each of which contains the working contents for a corresponding one of a plurality n of instruction threads. Timing and control circuitry is coupled to each of the principal processor components for controlling the timing and sequence of operations on instructions from the plurality n of instruction threads such that multiple instruction threads are separately handled substantially concurrently. Corresponding hybrid processing methods for such a single pipelined processor are also discussed.