Patents by Inventor Sebastian Ziesler

Sebastian Ziesler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8510626
    Abstract: Data encoding apparatus and methods are disclosed. A Cyclic Redundancy Check (CRC) coding module is selected, from a plurality of different CRC coding modules, for coding a block of information. A generic coder, which is configurable to perform CRC coding based on any of the plurality of different CRC coding modules, is configured to perform CRC coding for the block of information based on the selected CRC coding module. A block of information for which a coding operation is to be performed may be segmented into a plurality of segments having respective lengths. Respective generic coders may be configured to perform the coding operation for the plurality of segments. In this case, a result of the coding operation for the block of information may be determined based on results of the coding operations for the plurality of data segments.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: August 13, 2013
    Assignee: Cortina Systems, Inc.
    Inventors: Sebastian Ziesler, Aws Shallal
  • Publication number: 20120079347
    Abstract: Data encoding apparatus and methods are disclosed. A Cyclic Redundancy Check (CRC) coding module is selected, from a plurality of different CRC coding modules, for coding a block of information. A generic coder, which is configurable to perform CRC coding based on any of the plurality of different CRC coding modules, is configured to perform CRC coding for the block of information based on the selected CRC coding module. A block of information for which a coding operation is to be performed may be segmented into a plurality of segments having respective lengths. Respective generic coders may be configured to perform the coding operation for the plurality of segments. In this case, a result of the coding operation for the block of information may be determined based on results of the coding operations for the plurality of data segments.
    Type: Application
    Filed: December 8, 2011
    Publication date: March 29, 2012
    Inventors: Sebastian ZIESLER, Aws Shallal
  • Patent number: 8095846
    Abstract: Data encoding apparatus and methods are disclosed. A Cyclic Redundancy Check (CRC) coding module is selected, from a plurality of different CRC coding modules, for coding a block of information. A generic coder, which is configurable to perform CRC coding based on any of the plurality of different CRC coding modules, is configured to perform CRC coding for the block of information based on the selected CRC coding module. A block of information for which a coding operation is to be performed may be segmented into a plurality of segments having respective lengths. Respective generic coders may be configured to perform the coding operation for the plurality of segments. In this case, a result of the coding operation for the block of information may be determined based on results of the coding operations for the plurality of data segments.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: January 10, 2012
    Assignee: Cortina Systems, Inc.
    Inventors: Sebastian Ziesler, Aws Shallal
  • Publication number: 20080307288
    Abstract: Data encoding apparatus and methods are disclosed. A Cyclic Redundancy Check (CRC) coding module is selected, from a plurality of different CRC coding modules, for coding a block of information. A generic coder, which is configurable to perform CRC coding based on any of the plurality of different CRC coding modules, is configured to perform CRC coding for the block of information based on the selected CRC coding module. A block of information for which a coding operation is to be performed may be segmented into a plurality of segments having respective lengths. Respective generic coders may be configured to perform the coding operation for the plurality of segments. In this case, a result of the coding operation for the block of information may be determined based on results of the coding operations for the plurality of data segments.
    Type: Application
    Filed: June 8, 2007
    Publication date: December 11, 2008
    Inventors: Sebastian Ziesler, Aws Shallal
  • Publication number: 20050262329
    Abstract: A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible with a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. Switching between 16-bit instruction execution and 32-bit instruction execution is accomplished by branch instructions that employ a least significant bit position of the address of the target of the branch to identify whether the target instruction is a 16-bit instruction or a 32-bit instruction.
    Type: Application
    Filed: August 19, 2003
    Publication date: November 24, 2005
    Applicant: Hitachi, Ltd.
    Inventors: Sivaram Krishnan, Mark Debbage, Sebastian Ziesler, Kanad Roy, Andrew Sturges, Prasenjit Biswas