Abstract: A signal receiver (300) has a tuner (301), which receives an RF_IN signal and outputs a desired IF_OUT intermediate frequency signal to a demodulator (311). The demodulator (311), on the basis of the signal level received from the tuner and the AGC characteristic set by a processor (321), controls the RF_AGC and IF_AGC tuner gains. The demodulator operation may also base on the signal level read from the IF_OUT output of the IF_Amp amplifier. The demodulator (311) sends to the processor (321) a digital stream of a desired signal TS. The processor comprises an AGC characteristic controller (327) for calculating the AGC characteristic of the tuner on the basis of a level of the desired signal and a strongest level of close signals, which are detected within the passband of the input filter (101) of the tuner (301) for the desired signal.

Abstract: A signal receiver (300) has a tuner (301), which receives an RF_IN signal and outputs a desired IF_OUT intermediate frequency signal to a demodulator (311). The demodulator (311) controls the RF_AGC and IF_AGC tuner gains according to an AGC characteristic of the tuner, to provide a constant level of the IF_OUT signal. The demodulator (311) sends to the processor (321) a digital stream of a desired signal TS. The processor comprises an AGC characteristic controller (327) for calculating the AGC characteristic of the tuner on the basis of a level of the desired signal and a strongest level of close signals, which are detected within the passband of the input filter (101) of the tuner (301) for the desired signal.

Abstract: A device for checking numbers consists of a multiplexer (101) with a controller module (106) linked to it. An output of the multiplexer is connected to a first input of a register (102), which is an element of memory, while a first output of the controller module (106) is connected to an input of a memory (103) and a second input of the register (102). An output of the register (102) and an output of the memory (103) are connected to inputs of the adder (104), which adds on its output a number, stored in the register (102) and a number written in the memory (103) at an address indicated by the controller module (106). The adder (104) generates on its output a carry-out signal, informing about overflow, which is passed to a first controlling input of the controller module (106), which manages operation of the device checking numbers.

Abstract: A method for calibration of a signal receiver comprising automatic gain control circuits (201, 202, . . . ) from which at least one has unknown characteristic and at least one has a known characteristic, wherein the signal receiver output signal (S 2) is input to a calibration block (203), in which control signals (AGC 1, AGC 2, . . . ) are generated for each automatic gain control circuit (201, 202, . . .

Abstract: A method for calibration of a signal receiver comprising automatic gain control circuits (201, 202, . . . ) from which at least one has unknown characteristic and at least one has a known characteristic, wherein the signal receiver output signal (S 2) is input to a calibration block (203), in which control signals (AGC 1, AGC 2, . . . ) are generated for each automatic gain control circuit (201, 202, . . .

Abstract: A signal receiver (300) has a tuner (301), which receives an RF_IN signal and outputs a desired IF_OUT intermediate frequency signal to a demodulator (311). The demodulator (311) controls the RF_AGC and IF_AGC tuner gains according to an AGC characteristic of the tuner, to provide a constant level of the IF_OUT signal. The demodulator (311) sends to the processor (321) a digital stream of a desired signal TS. The processor comprises an AGC characteristic controller (327) for calculating the AGC characteristic of the tuner on the basis of a level of the desired signal and a strongest level of close signals, which are detected within the passband of the input filter (101) of the tuner (301) for the desired signal.

Abstract: A signal receiver (300) has a tuner (301), which receives an RF_IN signal and outputs a desired IF_OUT intermediate frequency signal to a demodulator (311). The demodulator (311), on the basis of the signal level received from the tuner and the AGC characteristic set by a processor (321), controls the RF_AGC and IF_AGC tuner gains. The demodulator operation may also base on the signal level read from the IF_OUT output of the IF_Amp amplifier. The demodulator (311) sends to the processor (321) a digital stream of a desired signal TS. The processor comprises an AGC characteristic controller (327) for calculating the AGC characteristic of the tuner on the basis of a level of the desired signal and a strongest level of close signals, which are detected within the passband of the input filter (101) of the tuner (301) for the desired signal.