Abstract: A circuit includes a plurality of logically identical clock modules which are all capable of driving the same clock output. The circuit has a selection input for selecting one of the clock modules for driving the clock output. After a change of the selection, a clock module just deselected awaits the completion of a period of the own clock signal before switching to deselection. The clock modules have a hold-off input which is coupled to a common signal line. A newly selected clock module switches to a selection state only after a beginning of a period of the own clock signal, provided that the selected clock module previously detects a signal on its hold-off input which indicates that all clock modules have deselected themselves. The common signal line is preferably coupled to the clock output, deselection being detected on the basis of the signal level which occurs after the beginning of the period after a change of the selection.