Abstract: In an embodiment, a method for processing instructions in a microcontroller is disclosed. In the embodiment, the method involves, upon receipt of an interrupt while an instruction is being executed, completing execution of the instruction by a shadow functional unit and, upon servicing the interrupt, terminating re-execution of the instruction and updating a main register file with the result of the execution of the instruction by the shadow functional unit.

Abstract: Self-regulating body-biasing techniques for Process, Voltage, and Temperature (PVT) fluctuation compensation in Fully-Depleted Silicon-on-Insulator (FDSOI) semiconductors are disclosed. In an illustrative, non-limiting embodiment, an electronic device may include a logic cell having a plurality of FDSOI transistors manufactured thereon; and at least one current source coupled to a body terminal of each transistor in a subset of the FDSOI transistors, wherein the current source is configured to output a high-impedance current.

Abstract: Self-regulating body-biasing techniques for Process, Voltage, and Temperature (PVT) fluctuation compensation in Fully-Depleted Silicon-on-Insulator (FDSOI) semiconductors are disclosed. In an illustrative, non-limiting embodiment, an electronic device may include a logic cell having a plurality of FDSOI transistors manufactured thereon; and at least one current source coupled to a body terminal of each transistor in a subset of the FDSOI transistors, wherein the current source is configured to output a high-impedance current.

Abstract: An electronic device includes a digital circuit, a power delivery subsystem configured to provide a supply voltage and a body-biasing voltage to the digital circuit, and a controller a controller coupled to the power delivery subsystem. The controller is configured to determine a process parameter for the electronic device, determine a current temperature parameter for the electronic device, concurrently determine a first coarse-grain level for the supply voltage and a second coarse-grain level for the body-biasing voltage based on the process parameter, the current temperature parameter, and a frequency of a clock signal to be supplied to the digital circuit, and to determine a fine-grain level for the supply voltage.

Abstract: An electronic device includes a digital circuit, a power delivery subsystem configured to provide a supply voltage and a body-biasing voltage to the digital circuit, and a controller a controller coupled to the power delivery subsystem. The controller is configured to determine a process parameter for the electronic device, determine a current temperature parameter for the electronic device, concurrently determine a first coarse-grain level for the supply voltage and a second coarse-grain level for the body-biasing voltage based on the process parameter, the current temperature parameter, and a frequency of a clock signal to be supplied to the digital circuit, and to determine a fine-grain level for the supply voltage.

Abstract: A level shifter circuit is described herein for shifting a signal from a first voltage domain to a second voltage domain. The level shifter circuit includes two current paths between a supply terminal of the first voltage domain and a supply terminal of the second voltage domain. The first and second current paths each include a differential transistor that receives a signal from a pulse generator in a first voltage domain. The pulse generator provides pulses to the differential transistors based on an input signal to be translated to the second voltage domain. The level shifter includes a latch circuit in the second voltage domain that includes two inputs where each input is biased at a node of one of the current paths. Each current path includes a bias transistor whose control terminal receives a compensated biasing voltage for biasing the bias transistor. The compensated biasing voltage is compensated to account for drive strength variation of at least one transistor in each current path.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.

Abstract: In an embodiment, a method for processing instructions in a microcontroller is disclosed. In the embodiment, the method involves, upon receipt of an interrupt while an instruction is being executed, completing execution of the instruction by a shadow functional unit and, upon servicing the interrupt, terminating re-execution of the instruction and updating a main register file with the result of the execution of the instruction by the shadow functional unit.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.