Patents by Inventor Sebastien Barnola
Sebastien Barnola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9240325Abstract: A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.Type: GrantFiled: September 26, 2014Date of Patent: January 19, 2016Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVESInventors: Sébastien Barnola, Yves Morand, Heimanu Niebojewski
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Patent number: 9156306Abstract: Lithography method for etching very dense patterns on a substrate, based on a combination of several less dense partial patterns; a sacrificial layer is formed on a substrate and is etched according to a first partial pattern; spacers are formed on edges of elements of the sacrificial layer, the spacers defining a second partial pattern; then the sacrificial layer is removed leaving only the spacers remaining. A layer sensitive to an electron beam is subsequently deposited between the spacers to a thickness less than or equal to the height of the spacers, and this sensitive layer is exposed using an electron beam according to a third partial pattern such that there remains on the substrate a final pattern of regions lacking spacers and a sensitive layer, this pattern resulting from the combination of the second and third partial patterns and having higher density than each of the partial patterns.Type: GrantFiled: May 25, 2011Date of Patent: October 13, 2015Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Laurent Pain, Jerome Belledent, Sebastien Barnola
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Publication number: 20150091106Abstract: A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.Type: ApplicationFiled: September 26, 2014Publication date: April 2, 2015Inventors: SÉBASTIEN BARNOLA, YVES MORAND, HEIMANU NIEBOJEWSKI
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Patent number: 8889550Abstract: A method of lithography for formation of two networks of conductors connected by vias in microelectronic integrated circuits comprises, after formation of a first network of buried conductors under an insulating layer: deposition and etching of a sacrificial layer on a substrate, formation of spacers along all edges of elements of the sacrificial layer; removal of this layer; etching of a masking layer. Then, two successive etchings of the insulating layer are carried out, over two successive depths, one defining the depth of the conductors of the second network, the other defining a complement of depth needed at the desired locations for the vias. One of the etchings is defined by the masking layer and corresponds to the locations of the conductors of the second network; the other is defined both by the spacers and by openings in a layer etched by lithography and corresponds to the locations of the vias.Type: GrantFiled: May 25, 2011Date of Patent: November 18, 2014Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Jerome Belledent, Laurent Pain, Sebastien Barnola
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Patent number: 8877622Abstract: A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones.Type: GrantFiled: July 22, 2011Date of Patent: November 4, 2014Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Thierry Poiroux, Sébastien Barnola, Yves Morand
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Publication number: 20140187035Abstract: The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O2) and/or nitrogen (N2) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SixHy for which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SixFy and SixCly, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.Type: ApplicationFiled: December 27, 2013Publication date: July 3, 2014Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, APPLIED MATERIALS, Inc., CNRS Centre National de la Recherche ScientifiqueInventors: Nicolas POSSEME, Sebastien BARNOLA, Olivier JOUBERT, Srinivas NEMANI, Laurent VALLIER
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Patent number: 8669188Abstract: The substrate is provided with a layer of first material, a first etching mask, a covering layer and a second etching mask. The covering layer has a covered main area and an uncovered secondary area. The secondary area of the covering layer is partially etched via the second etching mask to form a salient pattern. Lateral spacers are formed around the salient pattern defining a third etching mask. The second etching mask is eliminated. The covering layer is etched by means of the third etching mask to form a salient pattern in the covering layer and to uncover the first etching mask and the first material. The layer of first material is etched to form the pattern made from the first material.Type: GrantFiled: November 21, 2011Date of Patent: March 11, 2014Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Sebastien Barnola, Jerome Belledent
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Publication number: 20130309854Abstract: A substrate is successively provided with a support, an electrically insulating layer, and a semi-conductor material layer. A first protective mask completely covers a second area of the semi-conductor material layer and leaves a first area of the semi-conductor material layer uncovered. A second etching mask partially covers the first area and at least partially covers the second area, so as to define and separate a first area and a second area. Lateral spacers are formed on the lateral surfaces of the second etching mask so as to form a third etching mask. The semi-conductor material layer is etched by means of the third etching mask so as to form a pattern made from semi-conductor material in the first area, the first etching mask protecting the second area.Type: ApplicationFiled: May 15, 2013Publication date: November 21, 2013Inventors: Francois ANDRIEU, Sebastien BARNOLA, Jerome BELLEDENT
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Publication number: 20130252412Abstract: A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones.Type: ApplicationFiled: July 22, 2011Publication date: September 26, 2013Applicant: Commissariat a l' energie atomique et aux energies alternativesInventors: Thierry Poiroux, Sébastien Barnola, Yves Morand
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Publication number: 20130087527Abstract: Lithography method for etching very dense patterns on a substrate, based on a combination of several less dense partial patterns; a sacrificial layer is formed on a substrate and is etched according to a first partial pattern; spacers are formed on edges of elements of the sacrificial layer, the spacers defining a second partial pattern; then the sacrificial layer is removed leaving only the spacers remaining A layer sensitive to an electron beam is subsequently deposited between the spacers to a thickness less than or equal to the height of the spacers, and this sensitive layer is exposed using an electron beam according to a third partial pattern such that there remains on the substrate a final pattern of regions lacking spacers and a sensitive layer, this pattern resulting from the combination of the second and third partial patterns and having higher density than each of the partial patterns.Type: ApplicationFiled: May 25, 2011Publication date: April 11, 2013Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Laurent Pain, Jerome Belledent, Sebastien Barnola
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Publication number: 20130072017Abstract: A method of lithography for formation of two networks of conductors connected by vias in microelectronic integrated circuits comprises, after formation of a first network of buried conductors under an insulating layer: deposition and etching of a sacrificial layer on a substrate, formation of spacers along all edges of elements of the sacrificial layer; removal of this layer; etching of a masking layer. Then, two successive etchings of the insulating layer are carried out, over two successive depths, one defining the depth of the conductors of the second network, the other defining a complement of depth needed at the desired locations for the vias. One of the etchings is defined by the masking layer and corresponds to the locations of the conductors of the second network; the other is defined both by the spacers and by openings in a layer etched by lithography and corresponds to the locations of the vias.Type: ApplicationFiled: March 25, 2011Publication date: March 21, 2013Inventors: Jerome Belledent, Laurent Pain, Sebastien Barnola
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Publication number: 20120132616Abstract: The substrate is provided with a layer of first material, a first etching mask, a covering layer and a second etching mask. The covering layer has a covered main area and an uncovered secondary area. The secondary area of the covering layer is partially etched via the second etching mask to form a salient pattern. Lateral spacers are formed around the salient pattern defining a third etching mask. The second etching mask is eliminated. The covering layer is etched by means of the third etching mask to form a salient pattern in the covering layer and to uncover the first etching mask and the first material. The layer of first material is etched to form the pattern made from the first material.Type: ApplicationFiled: November 21, 2011Publication date: May 31, 2012Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Sébastien BARNOLA, Jérôme BELLEDENT