Patents by Inventor SEBASTIEN FABRIE

SEBASTIEN FABRIE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method, and a synchronous digital circuit, for preventing propagation of set-up timing data errors
    Patent number: 10534396
    Abstract: There is disclosed a synchronous digital circuit having a system clock and for processing a data signal, wherein the digital circuit comprises a data path, a hard macro having a macro input, a logic circuit in the data path upstream of the macro input and having a first part and a second part, the second part being immediately upstream of the macro input, a set-up timing error detector having an input, wherein the input is on the data path between the first part and the second part, and a timing correction unit, wherein the data transit time across the second part is equal to or less than one half of a clock period, and wherein the timing correction unit is configured to correct, in response to the set-up timing error detector detecting a set-up timing error, the detected set-up timing error before the data reaches the macro input.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 14, 2020
    Assignee: NXP USA, Inc.
    Inventors: Sebastien Fabrie, Juan Echeverri Escobar, Jose Pineda De Gyvez
  • METHOD, AND A SYNCHRONOUS DIGITAL CIRCUIT, FOR PREVENTING PROPAGATION OF SET-UP TIMING DATA ERRORS
    Publication number: 20180224886
    Abstract: There is disclosed a synchronous digital circuit having a system clock and for processing a data signal, wherein the digital circuit comprises a data path, a hard macro having a macro input, a logic circuit in the data path upstream of the macro input and having a first part and a second part, the second part being immediately upstream of the macro input, a set-up timing error detector having an input, wherein the input is on the data path between the first part and the second part, and a timing correction unit, wherein the data transit time across the second part is equal to or less than one half of a clock period, and wherein the timing correction unit is configured to correct, in response to the set-up timing error detector detecting a set-up timing error, the detected set-up timing error before the data reaches the macro input.
    Type: Application
    Filed: March 5, 2018
    Publication date: August 9, 2018
    Inventors: SEBASTIEN FABRIE, JUAN ECHEVERRI ESCOBAR, JOSE PINEDA DE GYVEZ