Patents by Inventor Sebastien GAREAU
Sebastien GAREAU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250038888Abstract: An apparatus for marking errors in FlexO/ZR data includes circuitry configured to receive an Open Forward Error Correction (OFEC) block, decode a plurality of checksums in a payload area of the OFEC block, detect errors in the payload area based on the decoded plurality of checksums, and mark the detected errors in the payload area. The plurality of checksums are added during adaptation of the FlexO/ZR data to the OFEC block.Type: ApplicationFiled: October 16, 2024Publication date: January 30, 2025Applicant: Ciena CorporationInventors: Sebastien Gareau, Jeffery Thomas Nichols
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Publication number: 20250023655Abstract: A sub-carrier multiplexing (SCM) system include a digital layer including circuitry configured to interface with a client via a client signal and to interface with a media layer via a plurality of constituent signals, that together comprise the client signal; and the media layer including sub-carrier multiplexing (SCM) with each sub-carrier configured to carry one of the plurality of constituent signals. The client signal can be an Ethernet signal, Optical Transport Network (OTN) signal, etc., and the plurality of constituent signals can be Flexible Ethernet (FlexE) layer signals, Flexible OTN (FlexO) layer signals, Metro Transport Network (MTN) layer signals, ZR layer signals, etc.Type: ApplicationFiled: January 22, 2024Publication date: January 16, 2025Applicant: Ciena CorporationInventors: Stephen Daniel Shew, Sebastien Gareau
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Patent number: 12149352Abstract: Systems and methods include receiving (51) blocks of data that has been Forward Error Correction (FEC) encoded via Open Forward Error Correction (OFEC) adaptation; decoding (52) the blocks of data; processing (53) checksum data that is included in padding data required in the OFEC adaptation, wherein the padding data is distributed across N rows of payload data; and determining (54) a location of any errors in the payload data based on the processed checksum data. The OFEC adaptation is for mapping the blocks of data into any of a FlexO structure, a ZR structure, and variants thereof, and the location of any errors can be used for error marking.Type: GrantFiled: November 2, 2021Date of Patent: November 19, 2024Assignee: Ciena CorporationInventors: Sebastien Gareau, Jeffery Thomas Nichols
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Patent number: 12107629Abstract: An optical module includes a transmitter assembly; a receiver assembly; and circuitry connected to the transmitter assembly and the receiver assembly, wherein the circuity is configured to, responsive to a test of delay in one or more of the transmitter assembly and the receiver assembly, store a delay value for one or more of the transmitter assembly and the receiver assembly, and, responsive to a query of the delay, provide the stored delay value for each of the transmitter assembly and the receiver assembly. The circuitry can be further configured to perform the test of delay via inserting an event that is used for timing detection at a corresponding receiver assembly.Type: GrantFiled: December 22, 2022Date of Patent: October 1, 2024Assignee: Ciena CorporationInventors: Eric S. Maniloff, Sebastien Gareau, Benard J. Rhody
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Patent number: 12034624Abstract: A node includes circuitry configured to create a sequence of encoded blocks with the blocks including i) data blocks from a plurality of clients and ii) overhead blocks, insert one or more Operations, Administration, and Maintenance (OAM) fields representing client overhead in the overhead blocks, wherein each client has corresponding client overhead, and transmit the sequence of encoded blocks in an order.Type: GrantFiled: February 17, 2021Date of Patent: July 9, 2024Assignee: Ciena CorporationInventor: Sebastien Gareau
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Publication number: 20240214074Abstract: An optical module includes a transmitter assembly; a receiver assembly; and circuitry connected to the transmitter assembly and the receiver assembly, wherein the circuity is configured to, responsive to a test of delay in one or more of the transmitter assembly and the receiver assembly, store a delay value for one or more of the transmitter assembly and the receiver assembly, and, responsive to a query of the delay, provide the stored delay value for each of the transmitter assembly and the receiver assembly. The circuitry can be further configured to perform the test of delay via inserting an event that is used for timing detection at a corresponding receiver assembly.Type: ApplicationFiled: December 22, 2022Publication date: June 27, 2024Inventors: Eric S. Maniloff, Sebastien Gareau, Benard J. Rhody
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Patent number: 11974079Abstract: A ZR or ZR+ interface includes circuitry configured to receive one or more client signals; and circuitry configured to transmit the one or more client signals as an aggregate signal in a Flexible Ethernet (FlexE) format in one of a ZR format and a ZR+ format, including a mapping indicative of how the one or more client signals are one of multiplexed and subrated into the aggregate signal. The aggregate signal can have a rate that does not correspond to a standard Ethernet Physical Medium Dependent (PMD). The FlexE format can include a plurality of FlexE instances with at least one of the FlexE instances having calendar slots removed for a subrating application.Type: GrantFiled: July 20, 2020Date of Patent: April 30, 2024Assignee: Ciena CorporationInventor: Sebastien Gareau
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Patent number: 11916661Abstract: Systems and methods for timing over a Metro Transport Networking (MTN) path include detecting a specific block in a stream of blocks, wherein each block is encoded based on a line code, and sampling an output of a clock to determine a timestamp reference based on detection of the specific block, and transmitting timing information based on the timestamp reference. The specific block can be a control block. The timing information can be transmitted via a Precision Time Protocol (PTP) message. The timing information can be transmitted via a plurality of subsequent specific blocks.Type: GrantFiled: June 27, 2019Date of Patent: February 27, 2024Assignee: Ciena CorporationInventors: Sebastien Gareau, Andrew McCarthy
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Publication number: 20240048235Abstract: Systems and methods include receiving (102) a plurality of symbols that are part of a defined Digital Signal Processing (DSP) frame for coherent optical communication, wherein the DSP frame structure has a messaging channel incorporated therein that includes a subset of the plurality of symbols; capturing (104) multiple samples of the messaging channel; and determining (106) a message in the messaging channel based on analysis of the multiple samples. The method can further include transmitting (108), in the messaging channel, a reply to the message with the reply being repeated multiple times. The analysis is performed prior to Forward Error Correction (FEC) decoding on the data path.Type: ApplicationFiled: December 9, 2021Publication date: February 8, 2024Inventors: Sebastien Gareau, Timothy James Creasy
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Publication number: 20240048234Abstract: An optical interface includes circuitry configured to operate the optical interface at a first rate, subsequent to a requirement to subrate the optical interface to a second rate, determine which services are affected, signal a partial failure for the one or more affected services, and operate the optical interface at a second rate that is less than the first rate. The optical interface can be a Flexible Optical (FlexO) or ZR interface.Type: ApplicationFiled: October 23, 2023Publication date: February 8, 2024Applicant: Ciena CorporationInventor: Sebastien Gareau
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Publication number: 20240007225Abstract: Systems and methods include receiving (51) blocks of data that has been Forward Error Correction (FEC) encoded via Open Forward Error Correction (OFEC) adaptation; decoding (52) the blocks of data; processing (53) checksum data that is included in padding data required in the OFEC adaptation, wherein the padding data is distributed across N rows of payload data; and determining (54) a location of any errors in the payload data based on the processed checksum data. The OFEC adaptation is for mapping the blocks of data into any of a FlexO structure, a ZR structure, and variants thereof, and the location of any errors can be used for error marking.Type: ApplicationFiled: November 2, 2021Publication date: January 4, 2024Inventors: Sebastien Gareau, Jeffery Thomas Nichols
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Patent number: 11843414Abstract: An optical interface includes circuitry configured to operate the optical interface at a first rate, subsequent to a requirement to suberate the optical interface to a second rate, determine which services are affected, signal a partial failure for the one or more affected services, and operate the optical interface at a second rate that is less than the first rate. The optical interface can be a Flexible Optical (FlexO) or ZR interface.Type: GrantFiled: March 10, 2021Date of Patent: December 12, 2023Assignee: Ciena CorporationInventor: Sebastien Gareau
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Patent number: 11695472Abstract: Systems and methods include determining which services in a single Optical Transport Unit Cn (OTUCn) that is transmitted in an optical network via a plurality of optical carriers are affected by failed one or more optical carriers of the plurality of optical carriers; continuing to operate the single OTUCn with unaffected one or more optical carriers of the plurality of optical carriers; and adjusting some or all of the services from the failed one or more optical carriers to the unaffected one or more optical carriers.Type: GrantFiled: November 3, 2020Date of Patent: July 4, 2023Assignee: Ciena CorporationInventors: Trevor John Ibach, Rahim Amarsi, Sebastien Gareau
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Patent number: 11695494Abstract: An asynchronous adaptation process includes receiving a first plurality of frames of a first interface group at a first rate, determining idle/stuffing data to be added in each of the first plurality of frames based on a second rate associated with a second plurality of frames of a second interface group, adding information about the idle/stuffing data in each frame of the first plurality of frames in a preceding frame, and transmitting the second plurality of frames of the second interface group with the idle/stuffing data included therein, wherein the second plurality of frames includes the first plurality of frames with the idle/stuffing data.Type: GrantFiled: June 29, 2021Date of Patent: July 4, 2023Assignee: Ciena CorporationInventors: Andrew McCarthy, Sebastien Gareau
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Patent number: 11658737Abstract: Systems and methods include receiving a plurality of symbols that are part of a defined Digital Signal Processing (DSP) frame for coherent optical communication, wherein the DSP frame structure has a messaging channel incorporated therein that includes a subset of the plurality of symbols; capturing multiple samples of the messaging channel; and determining a message in the messaging channel based on analysis of the multiple samples. The method can further include transmitting, in the messaging channel, a reply to the message with the reply being repeated multiple times. The analysis is performed prior to Forward Error Correction (FEC) decoding on the data path.Type: GrantFiled: July 23, 2021Date of Patent: May 23, 2023Assignee: Ciena CorporationInventors: Sebastien Gareau, Timothy James Creasy
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Patent number: 11646864Abstract: An optical module for use in an optical system is disclosed, the optical module implementing Precision Time Protocol (PTP) clock functionality therein. The optical module includes an electrical interface with the optical system; circuitry connected to the electrical interface and configured to implement a plurality of functions of functionality; an optical interface connected to the circuitry; and timing circuitry connected to the electrical interface and one or more of the plurality of functions, wherein the timing circuitry is configured to implement the PTP clock functionality.Type: GrantFiled: January 18, 2019Date of Patent: May 9, 2023Assignee: Ciena CorporationInventors: Daniel Claude Perras, Sebastien Gareau
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Publication number: 20230031796Abstract: Systems and methods include receiving a plurality of symbols that are part of a defined Digital Signal Processing (DSP) frame for coherent optical communication, wherein the DSP frame structure has a messaging channel incorporated therein that includes a subset of the plurality of symbols; capturing multiple samples of the messaging channel; and determining a message in the messaging channel based on analysis of the multiple samples. The method can further include transmitting, in the messaging channel, a reply to the message with the reply being repeated multiple times. The analysis is performed prior to Forward Error Correction (FEC) decoding on the data path.Type: ApplicationFiled: July 23, 2021Publication date: February 2, 2023Inventors: Sebastien Gareau, Timothy James Creasy
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Patent number: 11552722Abstract: A coherent optical modem includes an optical interface; and circuitry connected to the optical interface and configured to detect a first timing reference point in a transmit Digital Signal Processor (DSP) frame in a transmit direction from a first node to a second node, and detect a second timing reference point in a receive DSP frame in a receive direction from the second node to the first node, wherein the first timing reference point and the second timing reference point are determined based on a pattern in any DSP frame field including i) padding area, ii) a reserved area, and iii) a DSP Multi-Frame Alignment Signal (MFAS) area. The pattern can be input in select DSP frames for a time period that is greater than a time period for each DSP frame.Type: GrantFiled: December 10, 2020Date of Patent: January 10, 2023Assignee: Ciena CorporationInventors: Sebastien Gareau, Jeffery Thomas Nichols, Manoj Verghese, Andrew McCarthy
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Publication number: 20230006759Abstract: An asynchronous adaptation process includes receiving a first plurality of frames of a first interface group at a first rate, determining idle/stuffing data to be added in each of the first plurality of frames based on a second rate associated with a second plurality of frames of a second interface group, adding information about the idle/stuffing data in each frame of the first plurality of frames in a preceding frame, and transmitting the second plurality of frames of the second interface group with the idle/stuffing data included therein, wherein the second plurality of frames includes the first plurality of frames with the idle/stuffing data.Type: ApplicationFiled: June 29, 2021Publication date: January 5, 2023Inventors: Andrew McCarthy, Sebastien Gareau
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Publication number: 20220264204Abstract: A ZR or ZR+ interface includes circuitry configured to receive one or more client signals; and circuitry configured to transmit the one or more client signals as an aggregate signal in a Flexible Ethernet (FlexE) format in one of a ZR format and a ZR+ format, including a mapping indicative of how the one or more client signals are one of multiplexed and subrated into the aggregate signal. The aggregate signal can have a rate that does not correspond to a standard Ethernet Physical Medium Dependent (PMD). The FlexE format can include a plurality of FlexE instances with at least one of the FlexE instances having calendar slots removed for a subrating application.Type: ApplicationFiled: July 20, 2020Publication date: August 18, 2022Inventor: Sebastien Gareau