Patents by Inventor Sebastien Haezebrouck

Sebastien Haezebrouck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240063714
    Abstract: Methods, systems, and apparatus for power consumption control in an electronic system is disclosed. A voltage of a voltage rail coupled between a power management system and the electronic system to a power consumption trigger voltage is compared. Based on the voltage of the voltage rail being below the power consumption trigger voltage, power consumption by the electronic system is increased to reduce the voltage of the voltage rail during a power down of the electronic system. A voltage output by a power source which is provided as an input to the power management system is detected to be at a nominal voltage after increasing the power consumption. Based on the detection, a regulated voltage is provided to the voltage rail to power up the electronic system.
    Type: Application
    Filed: August 14, 2023
    Publication date: February 22, 2024
    Inventors: Vincent Aubineau, Michael Andreas Staudenmaier, Sebastien Haezebrouck
  • Patent number: 10831556
    Abstract: Various systems and methods for virtual CPU consolidation to avoid physical CPU contention between virtual machines are described herein. A processor system that includes multiple physical processors (PCPUs) includes a first virtual machine (VM) that includes multiple first virtual processors (VCPUs); a second VM that includes multiple second VCPUs; and a virtual machine monitor (VMM) to map individual ones of the first VCPUs to run on at least one of, individual PCPUs of a first subset of the PCPUs and individual PCPUs of a set of PCPUs that includes the first subset of the PCPUs and a second subset of the PCPUs, based at least in part upon compute capacity of the first subset of the PCPUs to run the first VCPUs, and to map individual ones of the second VCPUs to run on individual ones of the second subset of the PCPUs.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: November 10, 2020
    Assignee: Intel IP Corporation
    Inventors: Yuyang Du, Jian Sun, Yong Tong Chua, Mingqiu Sun, Sebastien Haezebrouck, Nicole Chalhoub, Premanand Sakarda, Richard Quinzio
  • Publication number: 20190004866
    Abstract: Various systems and methods for virtual CPU consolidation to avoid physical CPU contention between virtual machines are described herein. A processor system that includes multiple physical processors (PCPUs) includes a first virtual machine (VM) that includes multiple first virtual processors (VCPUs); a second VM that includes multiple second VCPUs; and a virtual machine monitor (VMM) to map individual ones of the first VCPUs to run on at least one of, individual PCPUs of a first subset of the PCPUs and individual PCPUs of a set of PCPUs that includes the first subset of the PCPUs and a second subset of the PCPUs, based at least in part upon compute capacity of the first subset of the PCPUs to run the first VCPUs, and to map individual ones of the second VCPUs to run on individual ones of the second subset of the PCPUs.
    Type: Application
    Filed: December 23, 2015
    Publication date: January 3, 2019
    Inventors: Yuyang Du, Jian Sun, Yong Tong Chua, Mingqui Sun, Sebastien Haezebrouck, Nicole Chalhoub, Premanand Sakarda, Richard Quinzio