Abstract: In a method for fabricating a flip-chip light emitting diode device, epitaxial layers are deposited on a sapphire growth substrate to produce an epitaxial wafer. A plurality of light emitting diode devices are fabricated on the epitaxial wafer. The epitaxial wafer is diced to generate a device die. The device die is flip chip bonded to a mount. The flip chip bonding includes securing the device die to the mount by bonding at least one electrode of the device die to at least one bonding pad of the mount. Subsequent to the flip chip bonding, the growth substrate of the device die is removed via the application of laser light.

Abstract: In a method for fabricating a flip-chip light emitting diode device, epitaxial layers are deposited on a sapphire growth substrate to produce an epitaxial wafer. A plurality of light emitting diode devices are fabricated on the epitaxial wafer. The epitaxial wafer is diced to generate a device die. The device die is flip chip bonded to a mount. The flip chip bonding includes securing the device die to the mount by bonding at least one electrode of the device die to at least one bonding pad of the mount. Subsequent to the flip chip bonding, the growth substrate of the device die is removed via the application of laser light.

Abstract: A light emitting diode (10) has a backside and a front-side with at least one n-type electrode (14) and at least one p-type electrode (12) disposed thereon defining a minimum electrodes separation (delectrodes). A bonding pad layer (50) includes at least one n-type bonding pad (64) and at least one p-type bonding pad (62) defining a minimum bonding pads separation (dpads) that is larger than the minimum electrodes separation (delectrodes). At least one fanning layer (30) interposed between the front-side of the light emitting diode (10) and the bonding pad layer (50) includes a plurality of electrically conductive paths passing through vias (34, 54) of a dielectric layer (32, 52) to provide electrical communication between the at least one n-type electrode (14) and the at least one n-type bonding pad (64) and between the at least one p-type electrode (12) and the at least one p-type bonding pad (62).

Abstract: A light emitting diode (10) has a backside and a front-side with at least one n-type electrode (14) and at least one p-type electrode (12) disposed thereon defining a minimum electrodes separation (delectrodes). A bonding pad layer (50) includes at least one n-type bonding pad (64) and at least one p-type bonding pad (62) defining a minimum bonding pads separation (dpads) that is larger than the minimum electrodes separation (delectrodes). At least one fanning layer (30) interposed between the front-side of the light emitting diode (10) and the bonding pad layer (50) includes a plurality of electrically conductive paths passing through vias (34, 54) of a dielectric layer (32, 52) to provide electrical communication between the at least one n-type electrode (14) and the at least one n-type bonding pad (64) and between the at least one p-type electrode (12) and the at least one p-type bonding pad (62).

Abstract: A sapphire wafer having a thickness greater than 125 microns and having devices disposed thereon is laser scribed to form a grid array pattern of laser scribe lines laser scribed into the sapphire wafer. The sapphire wafer is separated along the laser scribe lines to separate a plurality of device dice defined by the grid array pattern of laser scribe lines. Each device die includes (i) a device and (ii) a portion of the sapphire wafer having the thickness greater than 125 microns. In some embodiments, a GaN LED device die includes a GaN based LED device, and a sapphire substrate supporting the GaN based LED device. The sapphire substrate has: (i) a thickness greater than 125 microns effective for increased light extraction due to a lower critical angle for total internal reflection; and (ii) sides generated by laser scribing.

Abstract: Surface mount light emitting diode (LED) packages each contain a light emitting diode (LED) die (24). A plurality of arrays of openings are drilled into an electrically insulating sub-mount wafer (10). A metal is applied to the drilled openings to produce a plurality of via arrays (12). The LED dice (24) are flip-chip bonded onto a frontside (16) of the sub-mount wafer (10). The p-type and n-type contacts of each flip-chip bonded LED (24) electrically communicate with a solderable backside (18) of the sub-mount wafer (10) through a via array (12). A thermal conduction path (10, 12) is provided for thermally conducting heat from the flip-chip bonded LED dice (24) to the solderable backside (18) of the sub-mount wafer (10). Subsequent to the flip-chip bonding, the sub-mount wafer (10) is separated to produce the surface mount LED packages.

Abstract: A light emitting diode (10) has a backside and a front-side with at least one n-type electrode (14) and at least one p-type electrode (12) disposed thereon defining a minimum electrodes separation (delectrodes). A bonding pad layer (50) includes at least one n-type bonding pad (64) and at least one p-type bonding pad (62) defining a minimum bonding pads separation (dpads) that is larger than the minimum electrodes separation (delectrodes). At least one fanning layer (30) interposed between the front-side of the light emitting diode (10) and the bonding pad layer (50) includes a plurality of electrically conductive paths passing through vias (34, 54) of a dielectric layer (32, 52) to provide electrical communication between the at least one n-type electrode (14) and the at least one n-type bonding pad (64) and between the at least one p-type electrode (12) and the at least one p-type bonding pad (62).

Abstract: Surface mount light emitting diode (LED) packages each contain a light emitting diode (LED) die (24). A plurality of arrays of openings are drilled into an electrically insulating sub-mount wafer (10). A metal is applied to the drilled openings to produce a plurality of via arrays (12). The LED dice (24) are flip-chip bonded onto a frontside (16) of the sub-mount wafer (10). The p-type and n-type contacts of each flip-chip bonded LED (24) electrically communicate with a solderable backside (18) of the sub-mount wafer (10) through a via array (12). A thermal conduction path (10, 12) is provided for thermally conducting heat from the flip-chip bonded LED dice (24) to the solderable backside (18) of the sub-mount wafer (10). Subsequent to the flip-chip bonding, the sub-mount wafer (10) is separated to produce the surface mount LED packages.

Abstract: Surface mount light emitting diode (LED) packages each contain a light emitting diode (LED) die (24). A plurality of arrays of openings are drilled into an electrically insulating sub-mount wafer (10). A metal is applied to the drilled openings to produce a plurality of via arrays (12). The LED dice (24) are flip-chip bonded onto a frontside (16) of the sub-mount wafer (10). The p-type and n-type contacts of each flip-chip bonded LED (24) electrically communicate with a solderable backside (18) of the sub-mount wafer (10) through a via array (12). A thermal conduction path (10, 12) is provided for thermally conducting heat from the flip-chip bonded LED dice (24) to the solderable backside (18) of the sub-mount wafer (10). Subsequent to the flip-chip bonding, the sub-mount wafer (10) is separated to produce the surface mount LED packages.