Patents by Inventor Sebastien METZGER

Sebastien METZGER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD FOR TRANSFERRING DATA BETWEEN A FIRST DIGITAL DOMAIN AND A SECOND DIGITAL DOMAIN, AND CORRESPONDING SYSTEM ON A CHIP
    Publication number: 20230325336
    Abstract: The system on a chip includes at least a first digital domain configured to be reinitialized by a first reinitialization signal, a second digital domain and an interface circuit. The interface circuit includes a starting register in the first digital domain, a destination register in the second digital domain and a synchronization circuit in the first digital domain. The interface circuit is configured to transfer data from the starting register to the destination register upon command of a control signal transmitted by the synchronization circuit. The starting register and the synchronization circuit are configured to not be reinitialized by the first reinitialization signal.
    Type: Application
    Filed: April 11, 2023
    Publication date: October 12, 2023
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Nicolas SAUX, Sebastien METZGER, Herve CASSAGNES
  • Method for managing the supply of information, such as instructions, to a microprocessor, and a corresponding system
    Patent number: 11275589
    Abstract: A processor interacts with a memory set including a cache memory, a first memory storing at least a first piece of information in a first information group, and a second memory storing at least a second piece of information in a second information group. In response to a first cache miss and following a first request from the processor for the first piece of information, the first piece of information obtained from the first memory is supplied to the processor. After a second request from the processor for the second piece of information, the second piece of information obtained from the second memory is supplied to the processor, even if the first information group is currently being transferred from the first memory for loading into the cache memory.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 15, 2022
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Sebastien Metzger, Silvia Brini
  • METHOD FOR MANAGING THE SUPPLY OF INFORMATION, SUCH AS INSTRUCTIONS, TO A MICROPROCESSOR, AND A CORRESPONDING SYSTEM
    Publication number: 20200097294
    Abstract: A processor interacts with a memory set including a cache memory, a first memory storing at least a first piece of information in a first information group, and a second memory storing at least a second piece of information in a second information group. In response to a first cache miss and following a first request from the processor for the first piece of information, the first piece of information obtained from the first memory is supplied to the processor. After a second request from the processor for the second piece of information, the second piece of information obtained from the second memory is supplied to the processor, even if the first information group is currently being transferred from the first memory for loading into the cache memory.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 26, 2020
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Sebastien METZGER, Silvia BRINI