Abstract: A power allocation strategy limits performance of a subset of a plurality of computational units in a computer system according to performance sensitivity of each of the plurality of computational units to a change performance capability, e.g., frequency change. The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state. The subset whose performance is limited includes computational units that are least performance sensitive according to stored sensitivity data. The subset may include one or more processing cores and performance of the one or more processing cores may be limited in response to a CPU-bounded application or graphics processing unit (GPU)-bounded application being executed.

Abstract: Methods, systems, and computer readable media for preemptive context-switching of processes on an accelerated processing device are based upon a comparison of the running time of the process and a threshold time quanta. A method includes preempting a process running on an accelerated processing device based upon a running time of the process and a threshold time quanta.

Abstract: Methods, systems, and computer readable media embodiments are disclosed for preemptive context-switching of processes running on an accelerated processing device. A method includes, responsive to an exception upon access to a memory by a process running on a accelerated processing device, whether to preempt the process based on the exception, and preempting, based upon the determining, the process from running on the accelerated processing device.

Abstract: Provided herein is a method including receiving a run list including one or more processes to run on an accelerated processing device, wherein each of the one or more processes is associated with a corresponding independent job command queue. The method also includes scheduling each of the one or more processes to run on the accelerated processing device based on a criteria associated with each process.

Abstract: Methods, systems, and computer readable media embodiments are disclosed for preemptive context-switching of processes running on a accelerated processing device. Embodiments include, detecting by an accelerated processing device a memory exception, and preempting a process from running on the accelerated processing device based upon the detected exception.

Abstract: Embodiments described herein provide a method of arbitrating a processing resource. The method includes receiving a command to preempt a task and preventing additional wavefronts associated with the task from being processed.

Abstract: Embodiments of the present invention provide a method of preempting a task. The method includes removing the task from the parallel processors via a scheduling mechanism. Responsive to the removing, the method also includes ceasing (i) retrieval of commands from a buffer associated with the task, (ii) dispatch of groups of work-items associated with the task, (iii) dispatch of wavefronts associated with the task, and (iiii) execution of the wavefronts. State information related to the task is saved.

Abstract: Embodiments of the present invention provide a method of synchronous operation of a first processing device and a second processing device. The method includes executing a process on the first processing device, responsive to a determination that execution of the process on the first device has reached a serial-parallel boundary, passing an execution thread of the process from the first processing device to the second processing device, and executing the process on the second processing device.

Abstract: Embodiments described herein provide a method including receiving a command to schedule a first process and selecting a command queue associated with the first process. The method also includes scheduling the first process to run on an accelerated processing device and preempting a second process running on the accelerated processing device to allow the first process to run on the accelerated processing device.

Abstract: Dynamic power test slave (DPTS) modules are placed at selected locations of a data processing device to provide data to a logic module of the device at a high rate during testing of the device. The DPTS module intercepts data requests targeted to another logic module and the DPTS instead provides the requested data, thus simulating data transfer by the target logic module. The simulated data transfers can provide for transitions at the data processing device from a relatively high power state to a relatively low power state. Accordingly, the DPTS modules allow for simulation of expected normal operating conditions during testing of the data processing device.

Abstract: Performance sensitivities to a change in performance capabilities of computational units of a computer system are determined based on measured utilization metrics for each of the computational units. In order to determine the performance sensitivities, in one approach, the computational units are operated at a first performance level, and respective first utilization metrics are determined. The computational units are then operated at a second performance level and respective second utilization metrics are determined. The sensitivity to performance capability change, e.g., a frequency change, is determined based on the respective first and second utilization metrics. The performance sensitivities of the computational units to a change in performance capability are continually updated in response to, e.g.

Abstract: A power allocation strategy limits performance of a subset of a plurality of computational units in a computer system according to performance sensitivity of each of the plurality of computational units to a change performance capability, e.g., frequency change. The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state. The subset whose performance is limited includes computational units that are least performance sensitive according to stored sensitivity data. The subset may include one or more processing cores and performance of the one or more processing cores may be limited in response to a CPU-bounded application or graphics processing unit (GPU)-bounded application being executed.

Abstract: One or more computational units of a computer system are selectively altered in terms of performance according to which of the one or more computational units has a higher performance sensitivity than others of the computational units.

Abstract: Requests to an operational module are received at a monitoring device, where an estimated amount of energy expected to be consumed by the operational module while executing operations related to requests is accumulated for a sliding time window. A throttle signal is generated to limit the amount of energy consumed by the operation module is generated when the accumulated amount exceeds a maximum amount.

Abstract: Processor overclocking techniques are disclosed. Upon automatically determining that overclocking entry criteria are satisfied, one or more cores are clocked above their standard operation frequencies. The cores may be overclocked until one or more exit criteria are satisfied. At that point, an exit procedure is performed, with the one or more overclocked cores return to their normal operating frequency.

Abstract: Requests to an operational module are received at a monitoring device, where an estimated amount of energy expected to be consumed by the operational module while executing operations related to requests is accumulated for a sliding time window.