Abstract: A transistor device (10), the transistor device (10) comprising a substrate (11, 14), a fin (3, 3A) aligned along a horizontal direction on the substrate (11, 14), a first source/drain region (4) of a first type of conductivity in the fin (3, 3A), a second source/drain region (5) of a second type of conductivity in the fin (3, 3A), wherein the first type of conductivity differs from the second type of conductivity, a channel region (33) in the fin (3, 3A) between the first source/drain region (4) and the second source/drain region (5), a gate insulator (6) on the channel region (33), and a gate structure (7, 8) on the gate insulator (6), wherein the sequence of the first source/drain region (4), the channel region (33) and the second source/drain region (5) is aligned along the horizontal direction.

Abstract: A device (100) for generating an output signal (So) having substantially same or increased output frequency compared to an input frequency of an input signal (Si), the device (100) comprising: a bipolar transistor (102) having a base (B), a collector (C), and an emitter (E); a control unit (104) adapted for controlling application of the input signal (Si) to the base (B) and adapted for controlling application of a collector-emitter voltage between the collector (C) and the emitter (E) in a manner for operating the bipolar transistor (102) in a snap-back regime to obtain a non-linear collector current characteristic to thereby generate the output signal (So) having the substantially same or increased output frequency resulting from a steeply rising collector current.

Abstract: The invention provides a three-dimensional stacked fin metal oxide semiconductor (SF-MOS) device (10,30) comprising a protrusion or fin structure with a plurality of stacked semiconductor regions (3,5,12), in which a second semiconductor region (5,12) is separated from a first semiconductor region (3,5) by an isolation region (4,11). A gate isolation layer (8) extends at least over the sidewalls of the protrusion (7) and a gate electrode extends over the gate isolation layer (8). The gate electrode comprises a plurality of gate regions (13,14,15) wherein each gate region (13,14,15) extends over another semiconductor region (3,5,12). In this way each gate region (13,14,15) influences the conduction channel of another semiconductor region (3,5,12) and hence adds another degree of freedom with which the performance of the SF-MOS device (10,30) can be optimized. The invention further provides a method of manufacturing the SF-MOS device (10,30) according to the invention.

Abstract: The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7).

Abstract: A device (100) for generating an output signal (So) having substantially same or increased output frequency compared to an input frequency of an input signal (Si), the device (100) comprising: a bipolar transistor (102) having a base (B), a collector (C), and an emitter (E); a control unit (104) adapted for controlling application of the input signal (Si) to the base (B) and adapted for controlling application of a collector-emitter voltage between the collector (C) and the emitter (E) in a manner for operating the bipolar transistor (102) in a snap-back regime to obtain a non-linear collector current characteristic to thereby generate the output signal (So) having the substantially same or increased output frequency resulting from a steeply rising collector current.

Abstract: A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region (18) is formed and patterned, base contact regions (26) formed on either side, and a gap formed between the base contact region. A base (28), spacers (30) and an emitter (32) are formed in the gap.

Abstract: A method of making a FET includes forming a gate structure (18), then etching cavities on either side. A SiGe layer (22) is then deposited on the substrate (10) in the cavities, followed by an Si layer (24). A selective etch is then carried out to etch away the SiGe (22) except for a part of the layer under the gate structure (18), and oxide (28) is grown to fill the resulting gap. SiGe source and drains are then deposited in the cavities. The oxide (28) can reduce junction leakage current.

Abstract: Consistent with an example embodiment, there is a bipolar transistor with a reduced collector series resistance integrated in a trench of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region with a first part on a selected portion of the collector region (6, 34), which is on the bottom of the trench, and an emitter region on a selected portion of the first part of the base region. A base contact electrically contacts the base region on a second part of the base region, which is on an insulating region. The collector region is electrically contacted on top of a protrusion with a collector contact.

Abstract: A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region (18) is formed and patterned, base contact regions (26) formed on either side, and a gap formed between the base contact region. A base (28), spacers (30) and an emitter (32) are formed in the gap.

Abstract: The invention relates to a method of manufacturing a semiconductor device comprising a field effect transistor, in which method a semiconductor body of silicon with a substrate is provided at a surface thereof with a source region and a drain region of a first conductivity type which are situated above a buried isolation region and with a channel region, between the source and drain regions, of a second conductivity type, opposite to the first conductivity type, and with a gate region separated from the surface of the semiconductor body by a gate dielectric and situated above the channel region, wherein a mesa is formed in the semiconductor body in which the channel region is formed and wherein the source and drain regions are formed on both sides of the mesa in a semiconductor region that is formed using epitaxial growth, the source and drain regions thereby contacting the channel region.

Abstract: The invention provides a three-dimensional stacked fin metal oxide semiconductor (SF-MOS) device (10,30) comprising a protrusion or fin structure with a plurality of stacked semiconductor regions (3,5,12), in which a second semiconductor region (5,12) is separated from a first semiconductor region (3,5) by an isolation region (4,11). A gate isolation layer (8) extends at least over the sidewalls of the protrusion (7) and a gate electrode extends over the gate isolation layer (8). The gate electrode comprises a plurality of gate regions (13,14,15) wherein each gate region (13,14,15) extends over another semiconductor region (3,5,12). In this way each gate region (13,14,15) influences the conduction channel of another semiconductor region (3,5,12) and hence adds another degree of freedom with which the performance of the SF-MOS device (10,30) can be optimized. The invention further provides a method of manufacturing the SF-MOS device (10,30) according to the invention.

Abstract: A transistor device (10), the transistor device (10) comprising a substrate (11, 14), a fin (3, 3A) aligned along a horizontal direction on the substrate (11, 14), a first source/drain region (4) of a first type of conductivity in the fin (3, 3A), a second source/drain region (5) of a second type of conductivity in the fin (3, 3A), wherein the first type of conductivity differs from the second type of conductivity, a channel region (33) in the fin (3, 3A) between the first source/drain region (4) and the second source/drain region (5), a gate insulator (6) on the channel region (33), and a gate structure (7, 8) on the gate insulator (6), wherein the sequence of the first source/drain region (4), the channel region (33) and the second source/drain region (5) is aligned along the horizontal direction.

Abstract: The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7).

Abstract: A method of making a FET includes forming a gate structure (18), then etching cavities on either side. A SiGe layer (22) is then deposited on the substrate (10) in the cavities, followed by an Si layer (24). A selective etch is then carried out to etch away the SiGe (22) except for a part of the layer under the gate structure (18), and oxide (28) is grown to fill the resulting gap. SiGe source and drains are then deposited in the cavities. The oxide (28) can reduce junction leakage current.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) comprising a field effect transistor, in which method a semiconductor body of silicon (12) with a substrate (11) is provided at a surface thereof with a source region (1) and a drain region (2) of a first conductivity type which are situated above a buried isolation region (3,4) and with a channel region (5), between the source and drain regions (1,2), of a second conductivity type, opposite to the first conductivity type, and with a gate region (6) separated from the surface of the semiconductor body (12) by a gate dielectric (7) and situated above the channel region (5), and wherein a mesa (M) is formed in the semiconductor body (12) in which the channel region (5) is formed and wherein the source and drain regions (1,2) are formed on both sides of the mesa (M) in a semiconductor region (8) that is formed using epitaxial growth, the source and drain regions (1,2) thereby contacting the channel region (5).

Abstract: Disclosed is an ultra wide band signal generator. The ultra wide band signal generator generates a signal of a required frequency using a harmonic signal having a frequency range of a ultra wide band (UWB). The ultra wide band signal generator includes an active inductor for generating harmonic signals having power strengths substantially equal to each other within a non-linear operation range, the tunable active inductor capable of tuning a value thereof, an oscillator for amplifying and outputting the harmonic signals generated from the active inductor by frequency-transiting the harmonic signals into high frequency bands, and a filter for selectively outputting one of the harmonic signals output from the oscillator.

Abstract: An active inductor capable of tuning a self-resonant frequency, an inductance, a Q factor, and a peak Q frequency by applying a tunable feedback resistor to a cascode-grounded active inductor is disclosed. The tunable active inductor includes a first transistor having a source connected to a power supply voltage and a gate connected to first bias voltage; a second transistor having a drain connected to a drain of the first transistor and a gate connected to a second bias voltage; a third transistor having a drain connected to a source of the second transistor and a source connected to a ground voltage; a fourth transistor having a drain connected to a gate of the third transistor, a source connected to the ground voltage and a gate connected to a third bias voltage; a fifth transistor having a source connected to the drain of the fourth transistor and a drain connected to the power supply voltage.

Abstract: Disclosed is an ultra wide band signal generator. The ultra wide band signal generator generates a signal of a required frequency using a harmonic signal having a frequency range of a ultra wide band (UWB). The ultra wide band signal generator includes an active inductor for generating harmonic signals having power strengths substantially equal to each other within a non-linear operation range, the tunable active inductor capable of tuning a value thereof, an oscillator for amplifying and outputting the harmonic signals generated from the active inductor by frequency-transiting the harmonic signals into high frequency bands, and a filter for selectively outputting one of the harmonic signals output from the oscillator.

Abstract: An active inductor capable of tuning a self-resonant frequency, an inductance, a Q factor, and a peak Q frequency by applying a tunable feedback resistor to a cascode-grounded active inductor is disclosed. The tunable active inductor includes a first transistor having a source connected to a power supply voltage and a gate connected to first bias voltage; a second transistor having a drain connected to a drain of the first transistor and a gate connected to a second bias voltage; a third transistor having a drain connected to a source of the second transistor and a source connected to a ground voltage; a fourth transistor having a drain connected to a gate of the third transistor, a source connected to the ground voltage and a gate connected to a third bias voltage; a fifth transistor having a source connected to the drain of the fourth transistor and a drain connected to the power supply voltage.