Abstract: The peak comparator circuitry comprises a differential amplifier circuit having an output node to generate a differential amplifier output signal in response to an amplification of a difference of an input signal and a reference signal, and a comparator circuit having an output node to generate a comparator output signal. A feedback path of the peak comparator circuitry is arranged between the output node of the comparator circuit and the output node of the differential amplifier circuit. The proposed peak comparator circuitry allows for a low voltage supply, a low current consumption and a fast output validity.

Abstract: In an embodiment a method includes providing an analog signal having a first value of a temperature of an object, performing an analog-to-digital conversion of the analog signal using a first analog-to-digital converter (ADC) thereby providing a first digital signal representing an initial digital temperature value, performing an analog-to-digital conversion of the analog signal using a second ADC thereby providing a second digital signal representing a digital reference temperature value, regularly providing the analog signal having a successive value of the temperature of the object, performing the analog-to-digital conversion of the analog signal using the second ADC thereby providing the second digital signal representing a successive digital temperature value, calculating a digital delta temperature value according to a difference between the successive digital temperature value and the digital reference temperature value and repeating portions of the method as long as the digital delta temperature value

Abstract: A current mirror arrangement includes an input stage with a series connection of an input mirror transistor and an input cascode transistor between supply terminals. A buffer stage is configured to generate an input control voltage based on an input voltage for a gate terminal of the input mirror transistor, to generate an intermediate control voltage at a replica terminal based on the input voltage and to generate a compensation control voltage based on the input control voltage, the buffer stageincluding a compensation current mirror with an input side connected to a feedback terminal and with an output side being connected to the replica terminal.

Abstract: In one embodiment a temperature sensor has a first sensing unit operable to provide a first pseudo-differential unipolar analog signal representing a first temperature value of a power unit, an interface circuit operable to provide a second pseudo-differential unipolar analog signal representing a second temperature value of a powered unit, a multiplexer circuit which is operable to provide a pseudo-differential unipolar multiplexed analog signal comprising the first analog signal or the second analog signal, and a first analog-to-digital converter, ADC, component operable to provide a first digital signal from the multiplexed analog signal, the first digital signal comprising a digital representation of the first analog signal or the second analog signal. Therein, the operation of the first ADC component is synchronized with a control signal designed for activating the power unit.

Abstract: In an embodiment a method includes providing an analog signal comprising a first value of a temperature of an object, performing an analog-to-digital conversion of the analog signal using a first analog-to-digital converter (ADC) thereby providing a first digital signal representing an initial digital temperature value, performing an analog-to-digital conversion of the analog signal using a second ADC thereby providing a second digital signal representing a digital reference temperature value, regularly providing the analog signal comprising a successive value of the temperature of the object, performing the analog-to-digital conversion of the analog signal using the second ADC thereby providing the second digital signal representing a successive digital temperature value, calculating a digital delta temperature value according to a difference between the successive digital temperature value and the digital reference temperature value and repeating providing the analog signal, performing the analog-to-digital

Abstract: A voltage conversion circuit comprises a first and a second output (O1, O2) which are configured to have an electric load (LD) connected therebetween, wherein an output signal between the first and a second output (O1, O2) is generated in response to a pulse-width modulated clock signal (PWM). The circuit further comprises a forward branch (FWD) being configured to generate an output voltage (VDC) at the first output (O1) depending on a control signal. A feedback branch (FBK) comprises a comparison circuit (CC) being configured to generate the control signal.

Abstract: A converter arrangement includes a converter device (200) with a clocked operating mode and a non-clocked operating mode, having a signal input (Si), a control input (Se), and a signal output (So), and a control device (100) for controlling the converter device (200) with a control signal of a constant frequency and at least minimal pulse length in the clocked operating mode. The control device (100) is coupled to the control input (Se) of the converter device (200), and an input of the control device (100) is coupled to the signal output (So) of the converter device (200). An input (1) of the converter arrangement supplies a signal to be converted, that is coupled to the signal input (Si) of the converter device (200). For providing a converted signal, the converter arrangement has an output (2) that is coupled to the signal output (So). Furthermore, a corresponding method for preparing a converted signal is disclosed.

Abstract: A voltage conversion circuit comprises a first and a second output (O1, O2) which are configured to have an electric load (LD) connected therebetween, wherein an output signal between the first and a second output (O1, O2) is generated in response to a pulse-width modulated clock signal (PWM). The circuit further comprises a forward branch (FWD) being configured to generate an output voltage (VDC) at the first output (O1) depending on a control signal. A feedback branch (FBK) comprises a comparison circuit (CC) being configured to generate the control signal.

Abstract: A converter arrangement includes a converter device (200) with a clocked operating mode and a non-clocked operating mode, having a signal input (Si), a control input (Se), and a signal output (So), and a control device (100) for controlling the converter device (200) with a control signal of a constant frequency and at least minimal pulse length in the clocked operating mode. The control device (100) is coupled to the control input (Se) of the converter device (200), and an input of the control device (100) is coupled to the signal output (So) of the converter device (200). An input (1) of the converter arrangement supplies a signal to be converted, that is coupled to the signal input (Si) of the converter device (200). For providing a converted signal, the converter arrangement has an output (2) that is coupled to the signal output (So). Furthermore, a corresponding method for preparing a converted signal is disclosed.

Abstract: The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Abstract: The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.