Abstract: A circuit comprises first, second, and third nodes (2002, 2004, 2006) respectively receiving a reference potential, a first voltage, and a second voltage. A first NMOS transistor has its gate connected to the second node. A second NMOS transistor has its drain and its source respectively connected to the source of the first transistor and to the second node. A third NMOS transistor has its gate and its source respectively connected to the second and first nodes. A fourth PMOS transistor has its drain connected to the drain of the third transistor and to the gate of the second transistor, and its gate connected to the source of the first transistor. A resistive element connects the first transistor to the third node, another resistive element connecting the fourth transistor to the third node.

Abstract: The present disclosure relates to a device (REFGEN) comprising: a first divider bridge (200) between a first node (202) at a supply voltage (VDDE) and a second node (204) at a reference potential (GND); a first transistor (Ten) and a second divider bridge (208) in series between the first and second nodes, the first transistor having its gate at the first bridge; a buffer circuit (BUFFa1) having an input (220) connected to a node (214) of the second bridge, and an output (218) delivering a reference voltage (VrefL); and a second transistor (To1) having its drain connected to the output of the buffer circuit, and its source connected to one of the first and second nodes. The first transistor (Ten) is OFF if the supply voltage (VDDE) is less than a threshold. The second transistor is ON if the first transistor is OFF, and vice versa.

Abstract: A method is provided for writing a data word to a resistive memory consisting of 2T2R differential cells each having first and second sets of a resistor (R) and a selection transistor (T). The method includes generating an initial codeword, programming it in 1T1R mode, checking its programming in 1T1R mode, inverting it, programming the inverted initial codeword in 1T1R mode, checking its programming in 1T1R mode, and reading, in 2T2R differential mode, that the read data correspond to said initial data. A device designed to implement this write method and to an electronic system including this device is also provided.