Patents by Inventor Sebastien Roger
Sebastien Roger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240234067Abstract: Electrical device comprising a body defining a closed inner space, a first electrode, a second electrode and a third electrode, a free end of each electrode opening inside the inner space, the free ends of each electrode being arranged, inside the inner space, apart from one another and opposite the other electrodes, the electrical device being configured to prohibit the current from flowing between the first electrode and the third electrode when the electric current or the electric voltage between the first electrode and the second electrode remains below a predefined threshold value; when the electric current or the electric voltage exceeds the threshold value, allow the current to flow between the first electrode and the third electrode.Type: ApplicationFiled: February 24, 2022Publication date: July 11, 2024Inventors: Arokiaraj ANDONISSAMY, Sébastien Roger Pierre DUBOC, Guillaume LEMMEL, Jean-François OEUVRARD
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Publication number: 20240136136Abstract: Electrical device comprising a body defining a closed inner space, a first electrode, a second electrode and a third electrode, a free end of each electrode opening inside the inner space, the free ends of each electrode being arranged, inside the inner space, apart from one another and opposite the other electrodes, the electrical device being configured to prohibit the current from flowing between the first electrode and the third electrode when the electric current or the electric voltage between the first electrode and the second electrode remains below a predefined threshold value; when the electric current or the electric voltage exceeds the threshold value, allow the current to flow between the first electrode and the third electrode.Type: ApplicationFiled: February 24, 2022Publication date: April 25, 2024Inventors: Arokiaraj ANDONISSAMY, Sébastien Roger Pierre DUBOC, Guillaume LEMMEL, Jean-François OEUVRARD
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Patent number: 11775716Abstract: A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.Type: GrantFiled: January 28, 2021Date of Patent: October 3, 2023Assignee: Synopsys, Inc.Inventors: Arturo Salz, Ching-Ping Chou, Jean-Philippe Colrat, Sébastien Roger Delerse, Luc Francois Vidal, Arnold Mbotchak
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Patent number: 11660863Abstract: A manifold component for a droplet ejection head, the manifold component comprising: a mount for receiving an actuator component that provides one or more rows of fluid chambers, each chamber being provided with a respective at least one actuating element and a respective at least one nozzle, the at least one actuating element for each chamber being actuable to eject a droplet of fluid in an ejection direction through the corresponding at least one nozzle, each row extending in a row direction; a manifold chamber, which extends from a first end to a second end, and widens from said first end to said second end, the second end providing fluidic connection, in parallel, to at least a group of chambers within said one or more rows and being located adjacent said mount; and at least one port, each port opening into the manifold chamber at the first end thereof; wherein at least one portion between the first end and second end of the manifold chamber is shaped as a hyperbolic acoustic horn.Type: GrantFiled: July 26, 2019Date of Patent: May 30, 2023Assignee: Xaar Technology LimitedInventors: Sebastien Roger Gabriel Degraeve, Colin Brook
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Patent number: 11493154Abstract: A threaded tubular connection comprises a first tubular component and a second tubular component. The first tubular component includes a female portion defined on an interior surface of the first tubular component. The female portion includes an inner threaded portion and an outer threaded portion which are offset radially with respect to a longitudinal axis of the first tubular component by a first shoulder. The second tubular component includes a male portion defined on an exterior surface of the second tubular component. The male portion is to be inserted into the female portion, and includes an inner threaded portion and an outer threaded portion which are offset radially with respect to a longitudinal axis of the second tubular component by a second shoulder. The second shoulder is to abut the first shoulder once the male portion is connected to the female portion.Type: GrantFiled: December 11, 2015Date of Patent: November 8, 2022Assignees: VALLOUREC OIL AND GAS FRANCE, NIPPON STEEL CORPORATIONInventors: Daly Daly, Alan Ford Fothergill, Sebastien Roger Claude Villert
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Patent number: 11298941Abstract: A manifold component for a droplet ejection head, the manifold component comprising: a mount for receiving at least one actuator component that provides one or more rows of fluid chambers, each chamber being provided with at least one respective actuating element and at least one respective nozzle, each at least one actuating element being actuable to eject a droplet of fluid in said ejection direction through the corresponding at least one of said nozzles, each row extending in a row direction; an inlet manifold chamber, which extends from a first end to a second end, the second end providing fluidic connection, in parallel, to at least a group of chambers within said one or more rows of fluid chambers and being located adjacent said mount; at least one inlet port, each inlet port opening into the inlet manifold chamber at the first end thereof; and a plurality of fluid guides disposed within the inlet manifold chamber, each fluid guide extending from a respective first end to a respective second end, the fiType: GrantFiled: July 26, 2019Date of Patent: April 12, 2022Assignee: Xaar Technology LimitedInventors: Sebastien Roger Gabriel Degraeve, Gareth Paul Neal
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Publication number: 20210291522Abstract: A manifold component for a droplet ejection head, the manifold component comprising: a mount for receiving an actuator component that provides one or more rows of fluid chambers, each chamber being provided with a respective at least one actuating element and a respective at least one nozzle, the at least one actuating element for each chamber being actuable to eject a droplet of fluid in an ejection direction through the corresponding at least one nozzle, each row extending in a row direction; a manifold chamber, which extends from a first end to a second end, and widens from said first end to said second end, the second end providing fluidic connection, in parallel, to at least a group of chambers within said one or more rows and being located adjacent said mount; and at least one port, each port opening into the manifold chamber at the first end thereof; wherein at least one portion between the first end and second end of the manifold chamber is shaped as a hyperbolic acoustic horn.Type: ApplicationFiled: July 26, 2019Publication date: September 23, 2021Inventors: Sebastien Roger Gabriel DEGRAEVE, Colin BROOK
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Publication number: 20210237443Abstract: A manifold component for a droplet ejection head, the manifold component comprising: a mount for receiving at least one actuator component that provides one or more rows of fluid chambers, each chamber being provided with at least one respective actuating element and at least one respective nozzle, each at least one actuating element being actuable to eject a droplet of fluid in said ejection direction through the corresponding at least one of said nozzles, each row extending in a row direction; an inlet manifold chamber, which extends from a first end to a second end, the second end providing fluidic connection, in parallel, to at least a group of chambers within said one or more rows of fluid chambers and being located adjacent said mount; at least one inlet port, each inlet port opening into the inlet manifold chamber at the first end thereof; and a plurality of fluid guides disposed within the inlet manifold chamber, each fluid guide extending from a respective first end to a respective second end, the fiType: ApplicationFiled: July 26, 2019Publication date: August 5, 2021Inventors: Sebastien Roger Gabriel DEGRAEVE, Gareth Paul NEAL
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Publication number: 20210150110Abstract: A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.Type: ApplicationFiled: January 28, 2021Publication date: May 20, 2021Inventors: Arturo SALZ, Ching-Ping Chou, Jean-Philippe Colrat, Sebastien Roger Delerse, Luc Francois Vidal, Arnold Mbotchak
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Patent number: 10949588Abstract: A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.Type: GrantFiled: November 10, 2017Date of Patent: March 16, 2021Assignee: SYNOPSYS, INC.Inventors: Arturo Salz, Ching-Ping Chou, Jean-Philippe Colrat, Sébastien Roger Delerse, Luc François Vidal, Arnold Mbotchak
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Patent number: 10489536Abstract: A hardware verification system according to one embodiment includes, in part, a plurality of programmable devices. The plurality of programmable devices include a master scheduler, a plurality of schedulers and a plurality of programmable delay elements. A first one of the plurality of schedulers is configured to receive one or more delay values associated with one or more of the plurality of delay elements. Each of the plurality of programmable delay elements corresponds to a delay. The first scheduler is further configured to send a parameter corresponding to the one or more delay values to the master scheduler, and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler.Type: GrantFiled: May 14, 2018Date of Patent: November 26, 2019Assignee: SYNOPSYS, INC.Inventors: Alexander Rabinovitch, Cedric Jean Alquier, Sébastien Roger Delerse
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Publication number: 20180260508Abstract: A hardware verification system according to one embodiment includes, in part, a plurality of programmable devices. The plurality of programmable devices include a master scheduler, a plurality of schedulers and a plurality of programmable delay elements. A first one of the plurality of schedulers is configured to receive one or more delay values associated with one or more of the plurality of delay elements. Each of the plurality of programmable delay elements corresponds to a delay. The first scheduler is further configured to send a parameter corresponding to the one or more delay values to the master scheduler, and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler.Type: ApplicationFiled: May 14, 2018Publication date: September 13, 2018Inventors: Alexander Rabinovitch, Cedric Jean Alquier, Sébastien Roger Delerse
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Publication number: 20170167641Abstract: A threaded tubular connection comprises a first tubular component and a second tubular component. The first tubular component includes a female portion defined on an interior surface of the first tubular component. The female portion includes an inner threaded portion and an outer threaded portion which are offset radially with respect to a longitudinal axis of the first tubular component by a first shoulder. The second tubular component includes a male portion defined on an exterior surface of the second tubular component. The male portion is to be inserted into the female portion, and includes an inner threaded portion and an outer threaded portion which are offset radially with respect to a longitudinal axis of the second tubular component by a second shoulder. The second shoulder is to abut the first shoulder once the male portion is connected to the female portion.Type: ApplicationFiled: December 11, 2015Publication date: June 15, 2017Applicants: VALLOUREC OIL AND GAS FRANCE, Nippon Steel & Sumitomo Metal CorporationInventors: Daly DALY, Alan Ford Fothergill, Sebastien Roger Claude VILLERT
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Patent number: 9547040Abstract: Embodiments relate to the emulation of circuits, and detecting an event in a plurality of signals in an emulated circuit. A host system incorporates global event detection logic into a design under test (DUT). An emulator emulates the DUT along with the incorporated global event detection logic. The global event detection logic divides one clock cycle of the DUT into multiple time periods. During each time period of the clock cycle, the emulator selects a different subset of signals from the plurality of signals of the DUT. The emulator determines whether an event occurred for a signal from the subset during the clock cycle. If an event is detected, the emulator generates an output indicating an event was detected among the plurality of signals.Type: GrantFiled: May 4, 2015Date of Patent: January 17, 2017Assignee: Synopsys, Inc.Inventors: Ludovic Marc Larzul, Frederic Maxime Emirian, Sebastien Roger Delerse
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Publication number: 20160327609Abstract: Embodiments relate to the emulation of circuits, and detecting an event in a plurality of signals in an emulated circuit. A host system incorporates global event detection logic into a design under test (DUT). An emulator emulates the DUT along with the incorporated global event detection logic. The global event detection logic divides one clock cycle of the DUT into multiple time periods. During each time period of the clock cycle, the emulator selects a different subset of signals from the plurality of signals of the DUT. The emulator determines whether an event occurred for a signal from the subset during the clock cycle. If an event is detected, the emulator generates an output indicating an event was detected among the plurality of signals.Type: ApplicationFiled: May 4, 2015Publication date: November 10, 2016Inventors: LUDOVIC MARC LARZUL, FREDERIC MAXIME EMIRIAN, SEBASTIEN ROGER DELERSE
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Publication number: 20150120880Abstract: The present invention concerns a system for accessing content stored on at least one server (5) of a secure local area network (20) from a device (1), said device (1) being connected to the local area network (20) via the Internet network (10), the system being characterised in that it comprises at least one publication server (3) connected to the device (1) via the Internet network (10) and an aggregation server (4) connected to said server (5) via the local area network (20); and in that, when the publication server (3) receives a request from the device (1) for access to said content of the server (5), the request comprising at least one valid connection identifier, said publication server (3) is capable of establishing a secure connection with said aggregation server (4); and in that the aggregation server (4) implements a content aggregation engine capable of collecting content from the server (5) via said local area network (20) on request, and of aggregating and then transmitting said collected contentType: ApplicationFiled: May 2, 2013Publication date: April 30, 2015Inventors: Christophe Du Laurent De La Barre, Guillaume Foltran, Nicolas Motron, Sebastien Roger