Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

Abstract: A method of writing in page mode in an electrically erasable and programmable non-volatile memory includes an initialization phase of writing an information element for the selection of the page in a storage latch associated with a column of the non-volatile memory array, and the writing in a temporary memory of each of the data bits to be written in the page. A write phase includes the selection of rows of the non-volatile memory array according to the contents of the temporary memory. A page mode write circuit includes one latch per column of the non-volatile memory array to contain a page selection information element, and a control logic circuit to give the row selection signals as a function of the contents of the temporary memory in a phase for writing the column of the non-volatile memory array.

Abstract: A serial input/output memory is able to read data in the memory upon reception of a partial read address in which there are N least significant bits lacking to form a complete address. The read-ahead step includes: simultaneously reading the P first bits of M words of the memory having the same partial address; when the received address is complete, selecting the P first bits of the word designated by the complete address and delivering these bits at the serial output of the memory; reading P following bits of the word designated by the complete address during the delivery of P previous bits and delivering these bits at the serial output of the memory when the P previous bits are delivered.

Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p-2q other data in the 2p-2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p-q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract: An integrated circuit serial access type memory, notably in EEPROM technology, includes a data input (DI) and a data output (DO), a defined memory plane (MM) organized in memory words, as well as a set (LAT) of column registers, one such register being associated with at least one memory word of the memory. The memory includes a writing circuit and/or a reading circuit. The writing circuit operates, during an operation for writing a binary word in a given memory word (M0-M7), for loading the binary data of the binary word received in series at the data input (DI) directly into respective storage and switching latches (HV0-HV7) of the column register (R1) associated with the memory word (M0-M7). The reading circuit operates, during an operation for reading a binary word in a memory word, for reading successively the binary data stored in the memory cells of the memory word and for delivering directly, in serial form, each binary data read to the data output (DO) of the memory.

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2P bits in the memory, where p is a non-zero whole number.

Abstract: The invention proposes a method of selecting a determined access line of a serial access type integrated circuit memory, a determined access line being selectable among a determined group of access lines (AL0-AL7) of the same nature, for example a group of bit lines or a group of word lines, a line code on p bits being respectively associated to each access line of the group, which consists in pre-activating all the access lines of the group, then ofdeactivating progressively the other access lines as a function of the bits (Ai) of the line code of the access line to select received in series via the serial data input of the memory such that, in the end, only the access line to be selected remains activated.

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p−2q other data in the 2p−2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p−q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract: An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel. The integrated circuit memory may include a buffer memory with a sufficient capacity to store a plurality of words, the output of which is coupled to the input of the FLASH memory. A circuit is also included for recording into the buffer memory a series of words to be recorded into the FLASH memory and recording into the FLASH memory the words first recorded into the buffer memory.

Abstract: A serial input/output memory is able to read data in the memory upon reception of a partial read address in which there are N least significant bits lacking to form a complete address. The read-ahead step includes: simultaneously reading the P first bits of M words of the memory having the same partial address; when the received address is complete, selecting the P first bits of the word designated by the complete address and delivering these bits at the serial output of the memory; reading P following bits of the word designated by the complete address during the delivery of P previous bits and delivering these bits at the serial output of the memory when the P previous bits are delivered.

Abstract: A device and method for the reading of cells of an EEPROM is provided. The device includes at least one reference cell and one circuit for comparison between a current flowing into the reference cell and a current flowing in a cell selected in read mode. The reference cell is in a programmed state. The programming of the reference cell is done after the control reading and during the integrated circuit power-on reset phase, activated by the powering on of the integrated circuit.

Abstract: A device for the resetting of a memory circuit in integrated circuit form includes means to recognize a particular sequence on one or more external signals applied to the integrated circuit, different from the sequences of operational functioning of the integrated circuit.

Abstract: Disclosed is a device for protection of stored data comprising protection means to control a signal to enable the programming of a memory, the programming being permitted when the enabling signal is in a first state and prohibited when the enabling signal is in a second state, the protection means including a supply voltage drop detection device to set the enabling signal in the second state when the supply voltage is below a threshold, said device further comprising a time delay circuit capable of setting the enabling signal in the second state during a given period when a control signal goes into a first state.

Abstract: A method for performing a first programming operation on a non-volatile memory device of the type that is normally programmed by executing a pre-programming erasure algorithm and then a programming algorithm. According to the method, a non-volatile memory device is manufactured with all its memory cells in the same state, and the first programming operation for setting the memory cells to desired states is performed by executing only the programming algorithm. In a preferred method, the memory device is provided with two modes of operation: a first mode in which programming is accomplished by executing the pre-programming erasure algorithm and then the programming algorithm, and a second mode in which programming is accomplished by executing only the programming algorithm. In the preferred method, the memory device is placed in the second mode of operation before the first programming operation is performed. A non-volatile memory device having two modes of operation is also provided.

Abstract: A parallel type of memory is divided into P sub-arrays with which there are associated column and row decoding circuits and read circuits. Circuits are used to produce and give P addresses simultaneously to the decoding circuits on the basis of a given address so as to enable the simultaneous reading of P words from a single address. Circuits receive the P information elements extracted from the P words and give them in series at an output port at a frequency greater than the reading frequency. Thus the access time to the information elements seen from the exterior of the memory is reduced.

Abstract: A non-volatile electrically erasable and programmable memory provides both a SDP (software data protection) function and an OTP (one-time protection) function. The memory comprises a memory array having a plurality of memory cells each for storing an information bit. The memory further comprises at least one supplementary cell for storing a first state bit pertaining to the write-accessible (or non-write accessible) state of all the memory cells of the memory array, and at least one other supplementary cell for storing a second state bit relating to the blank state (or non-blank state) of a group of memory cells designed to be programmed only once by the user. A common management circuit for the SDP and OTP cells is located outside the memory array.

Abstract: A method for the generation of voltage for the programming or erasure of a non-volatile memory cell is disclosed. Also disclosed is a circuit and a computer readable medium which implement the method. During an operation of programming or erasure in the memory, the slope P of the write voltage ramp is adapted to the number of memory cells to be programmed or erased simultaneously during this operation. This method is particularly useful in the field of non-volatile, electrically erasable and programmable memories.

Abstract: A voltage circuit generates a programming or erasure voltage for programming or erasing a floating-gate memory. The voltage generator circuit includes a charge pump to provide a pumped voltage and a shaping circuit to provide the programming or erasing voltage from the pumped voltage. A switching circuit enables the pumped voltage to reach a sufficient level before the shaping circuit generates the programming or erasure voltage.