Patents by Inventor Sedrak Sargisian

Sedrak Sargisian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for optimizing electronic design
    Patent number: 6446239
    Abstract: A system is disclosed for compacting an initial electronic layout of cells within an initial layout boundary. The system includes forming paths extending from a bottom edge of the layout to a top edge. The paths intersect cells of the initial layout. The system determines which of the paths are critical paths. Critical cuts are then determined. A critical cut is a cut that severs critical paths. A set of cells associated with a critical cut are removed from the layout and replaced in order to reduce the initial layout boundary.
    Type: Grant
    Filed: January 7, 1999
    Date of Patent: September 3, 2002
    Assignee: Monterey Design Systems, Inc.
    Inventors: Ara Markosian, Yaacov (Jacob) Greidinger, Siu-Tong Hui, Sedrak Sargisian