Abstract: A method and apparatus for optimizing crossover voltage for differential pair switches in a current-steering digital-to-analog converter or the like are disclosed. An array of at least one or more MOSFET switches may be utilized to control the crossover voltage of a differential pair of transistors such that the off time overlap of the differential pair transistors is optimized. In one embodiment, the pull-up and pull-down times of the input for the differential pair transistors are optimized such that the differential pair transistors are not turned off simultaneously. The array of switches may be n-channel MOSFETs when the differential pair are p-channel MOSFETs. Likewise, the array of switches may be p-channel MOSFETs when the differential pair are n-channel MOSFETs. The output of the diflerential pair is free of crossover glitches and is capable of being utilized in a data converter such as a current-steering digital-to-analog converter (DAC).

Abstract: The present invention provides for a shielded capacitor in a digital CMOS fabrication process. The shield capacitor comprises a first surface (also known as a top plate) and a second surface (the bottom plate). The bottom plate has two portions which are connected, and the two portions of the bottom plate are positioned to sandwich the top plate in between the portions. A polysilicon layer is fabricated between the plates and the substrate of the semiconductor to isolate the plates from the substrate. To build the shielded capacitor, the polysilicon layer is fabricated first, then the plates are built on top of the polysilicon layer. The polysilicon layer is silicized and is often connected to the ground.

Abstract: A novel signal processing scheme comprises a digital to analog converter which is clocked at a first frequency, and a switched capacitor filter which receives input from the digital to analog converter and is clocked at a second frequency which is a multiple N times the first frequency. A preferred version of the present invention further comprises an analog signal sychronization circuit which allows the switched capacitor filter to oversample output from the digital to analog converter. The analog signal sychronization circuit comprises a sample and hold circuit, which receives input from the digital to analog converter and holds the input so that the switched capacitor filter can sample the same input N times, and a digital clock generator, which clocks the sample and hold circuit such that the sample and hold circuit only samples settled and valid output data from the digital to analog converter.