Patents by Inventor See On Park

See On Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Floating gate based 3-terminal analog synapse device
    Patent number: 12237426
    Abstract: Provided is a floating gate based 3-terminal analog synapse device including a silicon channel layer; a gate oxide deposited on the silicon channel layer; a charge trap layer deposited on the gate oxide, wherein charges are injected into the charge trap layer; a barrier layer deposited on the charge trap layer, and having lower electron affinity than electron affinity of a material of the charge trap layer; and a gate metal layer deposited on an upper surface of the barrier layer, wherein a gate voltage is applied to the gate metal layer.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: February 25, 2025
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Shinhyun Choi, Beomjin Kim, Tae Ryong Kim, See On Park
  • METHOD AND ELECTRONIC CIRCUIT FOR MEMORY REPLACEMENT
    Publication number: 20250036572
    Abstract: A method and electronic circuit for memory replacement are provided. The method for memory replacement includes generating an input signal in response to an event for a memory, providing the input signal to a time-varying circuit including a plurality of time-varying devices, generating an output signal by reading a value stored in at least one time-varying device among the plurality of time-varying devices, and determining a storage space for replacement, based on the output signal.
    Type: Application
    Filed: November 16, 2023
    Publication date: January 30, 2025
    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Shinhyun CHOI, Myoungsoo Jung, Hakcheon Jeong, See-On Park, Donghyun Gouk, Seonghyeon Jang
  • MEMORY DEVICE AND MEMORY APPARATUS INCLUDING THE SAME
    Publication number: 20240365688
    Abstract: Disclosed are a memory device and a memory apparatus including the memory device. The memory device includes a first electrode, a second electrode spaced apart from the first electrode, and a resistance change layer arranged between the first electrode and the second electrode and doped with a halogen element in a metal oxide having an oxygen content that gradually changes from the second electrode to the first electrode.
    Type: Application
    Filed: May 31, 2023
    Publication date: October 31, 2024
    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Shinhyun CHOI, See-On PARK, Jongmin BAE, Hakcheon JEONG, Jongyong PARK
  • PHASE CHANGE RAM DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20240147875
    Abstract: Provided is a phase change RAM. The phase change RAM includes an electrode, a first layer located on the electrode, and a second layer located on the first layer. The first layer includes a locally formed phase change material region. In addition, a method of manufacturing a phase change RAM is provided. The method includes forming an electrode, forming a first layer on the electrode, forming a second layer on the first layer, and forming a phase change material region locally in the first layer due to a voltage applied to the second layer.
    Type: Application
    Filed: October 18, 2023
    Publication date: May 2, 2024
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Shinhyun CHOI, See-On PARK, Seok Man HONG
  • FLOATING GATE BASED 3-TERMINAL ANALOG SYNAPSE DEVICE AND A MANUFACTURING METHOD THEREOF
    Publication number: 20220285546
    Abstract: Provided is a floating gate based 3-terminal analog synapse device including a silicon channel layer; a gate oxide deposited on the silicon channel layer; a charge trap layer deposited on the gate oxide, wherein charges are injected into the charge trap layer; a barrier layer deposited on the charge trap layer, and having lower electron affinity than electron affinity of a material of the charge trap layer; and a gate metal layer deposited on an upper surface of the barrier layer, wherein a gate voltage is applied to the gate metal layer.
    Type: Application
    Filed: December 16, 2021
    Publication date: September 8, 2022
    Inventors: Shinhyun Choi, Beomjin Kim, Tae Ryong Kim, See On Park