Abstract: A system includes a first device and a second device coupled to a link including two or more data paths and a first portion and a second portion. The first device is to transmit a number of bits corresponding to a message before training the link on the first portion of the link, where the number of bits is equal to a number of the two or more data paths, and where each data path transmits one bit of the number of bits. The second device is to receive the message before training the link. The second device is to perform a decode operation on the number of bits received to determine the corresponding message and transmit a second message or data on the second portion of the link in response to performing the decode operation on the number of bits.

Abstract: A system includes a transmitter device and a receive device coupled to a link having data lanes. The receiver device includes training logic. Each of the plurality of data lanes is to receive, from the transmitter device, an incoming data stream having the same pattern repeated over the plurality of clock cycles, and the training logic is to shift the incoming data stream one unit interval (UI) at a time until a shifted data pattern matches an expected data pattern on each data lane. Each of the plurality of data lanes is to receive, from the transmitter device, a count value at every clock cycle, and the training logic is to shift one or more burst lengths (BLs) until each data lane receives a same count value, thereby synchronizing the data lanes to a common frame boundary.

Abstract: A device includes receiver circuitry to receive incoming signals on a clock lane and data lanes and detection circuitry. The detection circuitry is to monitor the incoming signals on the clock lane, and determine that an incoming pattern of the incoming signals on the clock lane does not correspond to a clock pattern associated with communicating data on the data lanes. The detection circuitry is to initiate a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern.

Abstract: A first device includes first circuitry to communicate with a second device over a first die-to-die (D2D) link, second circuitry to communicate with the second device over a second D2D link, and a link controller comprising logic to send first configuration data to the second device over the first D2D link. Responsive to determining that the first configuration data failed to configure the second device, the link controller comprises logic to send second configuration data to the second device over the second D2D link.

Abstract: A system includes a first device and a second device coupled to a link having one or more lanes. The first device is to transmit two or more frames to synchronize the one or more data lanes, where each frame comprises a quantity of bits. The second device is to receive a first set of bits from each data lane corresponding to the quantity of bits in each frame of the two or more frames. The second device is to determine that the first set of bits received from a data lane of the one or more data lanes does not correspond to a frame boundary of the two or more frames. The second device is further to synchronize each data lane of the one or more data lanes with respect to the frame boundary, responsive to determining that the first set of bits does not correspond to the frame boundary.

Abstract: Systems including a first circuit and a second circuit, with a multi-data lane link between the first circuit and the second circuit. The first circuit and the second circuit are configured to determine a delay setting of a clock signal forwarded from the first circuit to the second circuit by utilizing a first distinct subset of the data lanes to communicate commands redundantly encoded in multiple unit intervals of the data lanes and by utilizing a second distinct subset of the data lanes to communicate results of the commands.

Abstract: A device includes receiver circuitry to receive incoming signals on a clock lane and data lanes and detection circuitry. The detection circuitry is to monitor the incoming signals on the clock lane, and determine that an incoming pattern of the incoming signals on the clock lane does not correspond to a clock pattern associated with communicating data on the data lanes. The detection circuitry is to initiate a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern.

Abstract: A device includes receiver circuitry to receive incoming signals on a clock lane and data lanes and detection circuitry. The detection circuitry is to monitor the incoming signals on the clock lane, and determine that an incoming pattern of the incoming signals on the clock lane does not correspond to a clock pattern associated with communicating data on the data lanes. The detection circuitry is to initiate a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern.

Abstract: A system includes a link having one or more lanes associated with transmitting data and one or more lanes associated with transmitting a clock signal. The system includes a device coupled with the link, the device to receive a signal via the one or more lanes associated with transmitting the clock signal and determine a number of pulses associated with the signal over a period. The device is further to determine the number of pulses associated with the signal fail to satisfy a predetermined condition relating to a specified number of pulses for the period and initiate a power-down sequence in response to determining the number of pulses that fail to satisfy the predetermined condition relating to the specified number of pulses for the period.

Abstract: A system includes a first device and a second device coupled to a link having one or more lanes. The first device is to transmit two or more frames to synchronize the one or more data lanes, where each frame comprises a quantity of bits. The second device is to receive a first set of bits from each data lane corresponding to the quantity of bits in each frame of the two or more frames. The second device is to determine that the first set of bits received from a data lane of the one or more data lanes does not correspond to a frame boundary of the two or more frames. The second device is further to synchronize each data lane of the one or more data lanes with respect to the frame boundary, responsive to determining that the first set of bits does not correspond to the frame boundary.

Abstract: A system includes a first device and a second device coupled to a link having one or more lanes. The first device is to transmit two or more frames to synchronize the one or more data lanes, where each frame comprises a quantity of bits. The second device is to receive a first set of bits from each data lane corresponding to the quantity of bits in each frame of the two or more frames. The second device is to determine that the first set of bits received from a data lane of the one or more data lanes does not correspond to a frame boundary of the two or more frames. The second device is further to synchronize each data lane of the one or more data lanes with respect to the frame boundary, responsive to determining that the first set of bits does not correspond to the frame boundary.

Abstract: A system includes a first device and a second device coupled to a link including two or more data paths and a first portion and a second portion. The first device is to transmit a number of bits corresponding to a message before training the link on the first portion of the link, where the number of bits is equal to a number of the two or more data paths, and where each data path transmits one bit of the number of bits. The second device is to receive the message before training the link. The second device is to perform a decode operation on the number of bits received to determine the corresponding message and transmit a second message or data on the second portion of the link in response to performing the decode operation on the number of bits.

Abstract: A system includes a first device and a second device coupled to a link including two or more data paths and a first portion and a second portion. The first device is to transmit a number of bits corresponding to a message before training the link on the first portion of the link, where the number of bits is equal to a number of the two or more data paths, and where each data path transmits one bit of the number of bits. The second device is to receive the message before training the link. The second device is to perform a decode operation on the number of bits received to determine the corresponding message and transmit a second message or data on the second portion of the link in response to performing the decode operation on the number of bits.

Abstract: A system includes a transmitter to transmit a set of bits associated with signaling having one or more levels. The system includes a receiver coupled to the transmitter, the receiver to receive the set of bits and generate a first plurality of digital values, each digital value generated at a first timing value and a plurality of reference voltages, the reference voltage incremented based at least in part on generating a digital value of the first plurality of digital values. The receiver is to generate a second plurality of digital values at a second timing value and the plurality of reference voltages, the first timing value incremented to the second timing value based at least in part on generating the first plurality of digital values. The system includes a controller to determine an amplitude associated with each the first and second plurality of digital values.

Abstract: A system includes a link having one or more lanes associated with transmitting data and one or more lanes associated with transmitting a clock signal. The system includes a device coupled with the link, the device to receive a signal via the one or more lanes associated with transmitting the clock signal and determine a number of pulses associated with the signal over a period. The device is further to determine the number of pulses associated with the signal fail to satisfy a predetermined condition relating to a specified number of pulses for the period and initiate a power-down sequence in response to determining the number of pulses that fail to satisfy the predetermined condition relating to the specified number of pulses for the period.

Abstract: A system includes a first device and a second device coupled to a link including two or more data paths and a first portion and a second portion. The first device is to transmit a number of bits corresponding to a message before training the link on the first portion of the link, where the number of bits is equal to a number of the two or more data paths, and where each data path transmits one bit of the number of bits. The second device is to receive the message before training the link. The second device is to perform a decode operation on the number of bits received to determine the corresponding message and transmit a second message or data on the second portion of the link in response to performing the decode operation on the number of bits.

Abstract: A system includes a first device and a second device coupled to a link having one or more lanes. The first device is to transmit two or more frames to synchronize the one or more data lanes, where each frame comprises a quantity of bits. The second device is to receive a first set of bits from each data lane corresponding to the quantity of bits in each frame of the two or more frames. The second device is to determine that the first set of bits received from a data lane of the one or more data lanes does not correspond to a frame boundary of the two or more frames. The second device is further to synchronize each data lane of the one or more data lanes with respect to the frame boundary, responsive to determining that the first set of bits does not correspond to the frame boundary.

Abstract: A system includes a transmitter to transmit a set of bits associated with signaling having one or more levels. The system includes a receiver coupled to the transmitter, the receiver to receive the set of bits and generate a first plurality of digital values, each digital value generated at a first timing value and a plurality of reference voltages, the reference voltage incremented based at least in part on generating a digital value of the first plurality of digital values. The receiver is to generate a second plurality of digital values at a second timing value and the plurality of reference voltages, the first timing value incremented to the second timing value based at least in part on generating the first plurality of digital values. The system includes a controller to determine an amplitude associated with each the first and second plurality of digital values.

Abstract: A system includes a first device and a second device coupled to a link having one or more paths associated with transmitting a clock signal. The first device is to transmit a set of bits associated with a pattern via the one more paths. The set of bits are transmitted using a first clock signal having a first frequency less than a second frequency associated with data transmission operations. The second device is to receive the set of bits associated with the pattern, determine a number of pulses associated with the set of bits over a first period, and determine the number of pulses, associated with the set of bits, satisfies a predetermined condition relating to the number of pulses for the first period. The second device is to initiate a training of the link in response to determining the number of pulses satisfies the predetermined condition.

Abstract: The present disclosure includes a method of charging a battery. In one embodiment, the method comprises receiving, in a battery charging circuit on an electronic device, an input voltage having a first voltage value from an external power source. The battery charger is configured to produce a charge current having a first current value into the battery. The input current limit and/or duty cycle of the charger is monitored. Control signals may be generated to increase the first voltage value of the input voltage if either (i) the input current limit is activated or (ii) the duty cycle reaches a maximum duty cycle. The charger also receives signals indicating a temperature inside the electronic device and generates control signals to decrease the value of the input voltage when the temperature increases above a threshold temperature.