Abstract: An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.

Abstract: An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.

Abstract: Successive approximation register (SAR) analog-to-digital converters (ADCs) generally use one or more comparators to convert an analog signal to a digital signal. These comparators, however, can consume a great deal of power, so it is desirable to have a comparator configuration that consumes less power. Here, a multi-bandwidth comparator is provided, which can be switched between different coarse resolution and fine resolution. By using this single multi-bandwidth comparator, lower power consumption with a small amount of area can be achieved.

Abstract: Successive approximation register (SAR) analog-to-digital converters (ADCs) generally use one or more comparators to convert an analog signal to a digital signal. These comparators, however, can consume a great deal of power, so it is desirable to have a comparator configuration that consumes less power. Here, a multi-bandwidth comparator is provided, which can be switched between different coarse resolution and fine resolution. By using this single multi-bandwidth comparator, lower power consumption with a small amount of area can be achieved.

Abstract: Errors in an analog to digital converter that cause generated digital codes to deviate from expected values are corrected. A sample of an analog signal is stored in a storage element. An error signal is then generated, with the error signal representing a deviation of an expected digital code for the strength of a sample of an analog input from a value that would be generated without correction. The error signal is then added to the stored sample. In an embodiment implemented in the context of a SAR ADC, a digital value representing an integral non-linearity error is generated based on a partial digital code (result of a partial conversion of the sample) and an error coefficient. The digital value is converted to analog form by an auxiliary DAC, and added to the stored input sample.

Abstract: Errors in an analog to digital converter that cause generated digital codes to deviate from expected values are corrected. A sample of an analog signal is stored in a storage element. An error signal is then generated, with the error signal representing a deviation of an expected digital code for the strength of a sample of an analog input from a value that would be generated without correction. The error signal is then added to the stored sample. In an embodiment implemented in the context of a SAR ADC, a digital value representing an integral non-linearity error is generated based on a partial digital code (result of a partial conversion of the sample) and an error coefficient. The digital value is converted to analog form by an auxiliary DAC, and added to the stored input sample.

Abstract: An aspect of the invention improves accuracy of digital codes generated at the output of a SAR ADC by using multiple reference voltages. A first reference voltage is used to generate an equivalent voltage corresponding to previous resolved bits and a second reference voltage is used to generate equivalent voltage corresponding to the bits being presently resolved. Another aspect of the present invention provides an ADC with high SNR as well as high throughput performance. Such a feature may be achieved by resolving some of the MSBs of the digital code using a high speed and low SNR DAC and remaining bits of the digital code using a high SNR DAC.

Abstract: When converting an analog signal to N-bit digital codes, high SNR (signal to noise ratio) by generating multiple N-bit codes from the same analog sample and averaging the N-bit codes. However, the entire N-bit code is determined only a single time, and only P-bit (P less than N) codes are generated. The P-bit codes may be averaged, and the N-bit code is corrected based on the average value to generate an accurate N-bit digital code. As P can be much less than N, the correction can be implemented in a few iterations, thereby enabling the ADCs to be implemented with a high throughput performance. Due to the correction, a high SNR may be attained as well.

Abstract: When converting an analog signal to N-bit digital codes, high SNR (signal to noise ratio) by generating multiple N-bit codes from the same analog sample and averaging the N-bit codes. However, the entire N-bit code is determined only a single time, and only P-bit (P less than N) codes are generated. The P-bit codes may be averaged, and the N-bit code is corrected based on the average value to generate an accurate N-bit digital code. As P can be much less than N, the correction can be implemented in a few iterations, thereby enabling the ADCs to be implemented with a high throughput performance. Due to the correction, a high SNR may be attained as well.